A 16-Channel Fully Configurable Neural SoC With 1.52 μW/Ch Signal Acquisition, 2.79 μW/Ch Real-Time Spike Classifier, and 1.79 TOPS/W Deep Neural Network Accelerator in 22 nm FDSOI

With the advent of high-density micro-electrodes arrays, developing neural probes satisfying the real-time and stringent power-efficiency requirements becomes more challenging. A smart neural probe is an essential device in future neuroscientific research and medical applications. To realize such devices, we present a 22 nm FDSOI SoC with complex on-chip real-time data processing and training for neural signal analysis. It consists of a digitally-assisted 16-channel analog front-end with 1.52 μ W/Ch, dedicated bio-processing accelerators for spike detection and classification with 2.79 μ W/Ch, and a 125 MHz RISC-V CPU, utilizing adaptive body biasing at 0.5 V with a supporting 1.79 TOPS/W MAC array. The proposed SoC shows a proof-of-concept of how to realize a high-level integration of various on-chip accelerators to satisfy the neural probe requirements for modern applications

Advanced spike sorting approaches in implantable VLSI wireless brain computer interfaces: a survey

Brain Computer/Machine Interfaces (BCI/BMIs) have substantial potential for enhancing the lives of disabled individuals by restoring functionalities of missing body parts or allowing paralyzed individuals to regain speech and other motor capabilities. Due to severe health hazards arising from skull incisions required for wired BCI/BMIs, scientists are focusing on developing VLSI wireless BCI implants using biomaterials. However, significant challenges, like power efficiency and implant size, persist in creating reliable and efficient wireless BCI implants. With advanced spike sorting techniques, VLSI wireless BCI implants can function within the power and size constraints while maintaining neural spike classification accuracy. This study explores advanced spike sorting techniques to overcome these hurdles and enable VLSI wireless BCI/BMI implants to transmit data efficiently and achieve high accuracy.Comment: Submitted to 37th International Conference on VLSI Design 202

An Adaptive Neural Spike Processor With Embedded Active Learning for Improved Unsupervised Sorting Accuracy

There is a need for integrated spike sorting processors in implantable devices with low power consumption that have improved accuracy. Learning the characteristics of the variable input neural signals and adapting the functionality of the sorting process can improve the accuracy. An adaptive spike sorting processor is presented accounting for the variation in the input signal noise characteristics and the variable difficulty in the selection of the spike characteristics, which significantly improves the accuracy. The adaptive spike processor was fabricated in 180-nm CMOS technology for proof of concept. It performs conditional detection, alignment, adaptive feature extraction, and online clustering with sorting threshold self-tuning capability. The chip was tested under different input signal conditions to demonstrate its adaptation capability providing a median classification accuracy of 84.5 & #x0025; and consuming 148 & #x03BC;W from a 1.8 V supply voltage

Accurate, Very Low Computational Complexity Spike Sorting Using Unsupervised Matched Subspace Learning

This paper presents an adaptable dictionary-based feature extraction approach for spike sorting offering high accuracy and low computational complexity for implantable applications. It extracts and learns identifiable features from evolving subspaces through matched unsupervised subspace filtering. To provide compatibility with the strict constraints in implantable devices such as the chip area and power budget, the dictionary contains arrays of {-1, 0 and 1} and the algorithm need only process addition and subtraction operations. Three types of such dictionary were considered. To quantify and compare the performance of the resulting three feature extractors with existing systems, a neural signal simulator based on several different libraries was developed. For noise levels $\sigma_N$ between 0.05 and 0.3 and groups of 3 to 6 clusters, all three feature extractors provide robust high performance with average classification errors of less than 8% over five iterations, each consisting of 100 generated data segments. To our knowledge, the proposed adaptive feature extractors are the first able to classify reliably 6 clusters for implantable applications. An ASIC implementation of the best performing dictionary-based feature extractor was synthesized in a 65-nm CMOS process. It occupies an area of 0.09 mm2 and dissipates up to about 10.48 μW from a 1 V supply voltage, when operating with 8-bit resolution at 30 kHz operating frequency

A highly accurate spike sorting processor with reconfigurable embedded frames for unsupervised and adaptive analysis of neural signals

Future implantable devices demand ultra-low power consumption with self-calibration capability providing real-time processing of biomedical signals. This paper introduces an adaptive processing framework for highly accurate on-chip spike sorting processing by learning the signal model in the recorded neural data. The novel adaptive spike sorting processor employs dual thresholding detection, adaptive feature extraction and online clustering with sorting threshold self-tuning capability. A prototype chip was fabricated in 180 nm CMOS technology. It achieves 84.5% overall clustering accuracy, provides up to 240X data reduction and consumes 148 μW of power from a 1.8 V supply voltage

Algorithm and Hardware Co-Design for Local/Edge Computing

Advances in VLSI manufacturing and design technology over the decades have created many computing paradigms for disparate computing needs. With concerns for transmission cost, security, latency of centralized computing, edge/local computing are increasingly prevalent in the faster growing sectors like Internet-of-Things (IoT) and other sectors that require energy/connectivity autonomous systems such as biomedical and industrial applications. Energy and power efficient are the main design constraints in local and edge computing. While there exists a wide range of low power design techniques, they are often underutilized in custom circuit designs as the algorithms are developed independent of the hardware. Such compartmentalized design approach fails to take advantage of the many compatible algorithmic and hardware techniques that can improve the efficiency of the entire system. Algorithm hardware co-design is to explore the design space with whole stack awareness. The main goal of the algorithm hardware co-design methodology is the enablement and improvement of small form factor edge and local VLSI systems operating under strict constraints of area and energy efficiency. This thesis presents selected works of application specific digital and mixed-signal integrated circuit designs. The application space ranges from implantable biomedical devices to edge machine learning acceleration