Design techniques for time based data converters

Modern day CMOS processes are characterized by voltage scaling and geometry scaling. Geometry scaling helps reduce gate delays, thereby aiding in the design of data converters which use time based processing. Another artifact of geometry scaling is the increase in complexity of digital circuitry available on traditional analog ICs, as digital signal processing could be used to compensate for analog inaccuracies. Calibration assisted analog-to-digital converters(ADCs), software defined radio, digital phase locked loops, etc... have all gained from improvements in the digital processing available on chip. This thesis focusses on data converters which utilize the above features of modern day CMOS processes. The thesis is primarily divided into two parts. The first part focuses on a technique to convert the time information into a digital word. A high resolution time-to-digital converter (TDC) architecture is proposed which combines the principles of noise-shaping integrating quantizer and charge-pump to build a third-order delta-sigma TDC using a dedicated feedback DAC. Fabricated in a 0.13µm CMOS process, the prototype TDC achieves better than 71dB DR for a 2.8MHz signal bandwidth. The second part of the thesis proposes a blind digital calibration technique to remove non-linearity in any traditional ADC architectures. The proposed technique uses the concept of downsampling and orthogonality of sinusoidal waves to estimate the harmonic distortion in ADCs and can be used to calibrate multiple harmonics simultaneously. As a proof of concept, the algorithm is demonstrated on a first-order ring oscillator based delta-sigma ADC, whose performance is harmonic distortion limited. Built in 0.13µm CMOS process, the algorithm improves the SNDR of the ADC by 39dB while improving SFDR by 45 dB

Power efficient analog-to-digital converters using both voltage and time domain information

As advanced wired and wireless communication systems attempt to achieve higher performance, the demand for high resolution and wide signal bandwidth in their associated ADCs is strongly increased. Recently, time-domain quantization has drawn attention from its scalability in deep submicron CMOS processes. Furthermore, there are several interesting aspects of time-domain quantizer by processing the signal in time rather than only in voltage domain especially for power efficiency. This research focuses on developing a new architecture for power efficient, high resolution ADCs using both voltage and time domain information. As a first approach, a new ΔƩ ADC based on a noise-shaped two-step integrating quantizer which quantizes the signal in voltage and time domains is presented. Attaining an extra order of noise-shaping from the integrating quantizer, the proposed ΔƩ ADC manifests a second-order noise-shaping with a first-order loop filter. Furthermore, this quantizer provides an 8b uantization in itself, drastically reducing the oversampling requirement. The proposed ADC also incorporates a new feedback DAC topology that alleviates the feedback DAC complexity of a two-step 8b quantizer. The measured results of the prototype ADC implemented in a 0.13μm CMOS demonstrate peak SNDR of 70.7dB (11.5b ENOB) at 8.1mW power, with an 8x OSR at 80MHz sampling frequency. To further improve ADC performance, a Nyquist ADC based on a time-based pipelined TDC is also proposed as a second approach. In this work, a simple V-T conversion scheme with a cheap low gain amplifier in its first stage and a hybrid time-domain quantization stage based on simple charge pump and capacitive DAC in its backend stages, are also proposed to improve ADC linearity and power efficiency. Using voltage and time domain information, the proposed ADC architecture is beneficial for both resolution and power efficiency, with MSBs resolved in voltage domain and LSBs in time domain. The measured results of the prototype ADC implemented in a 0.13μm CMOS demonstrate peak SNDR of 69.3dB (11.2b ENOB) at 6.38mW power and 70MHz sampling frequency. The FOM is 38.2fJ/conversion-step

Time-based noise-shaping techniques for time-to-digital and analog-to-digital converters

In this dissertation, time-based signal processing techniques and their applications in oversampling and noise-shaping data converters are examined. These techniques demonstrate the ability to shift the burden of high performance analog circuits from the compressed voltage-domain to the augmented time-domain. First, the potential of high order noise-shaping and phase-domain feedback in time-to-digital converters (TDCs) is explored. A prototype phase reference, second-order continuous-time delta-sigma TDC for sensor applications was fabricated in 90nm CMOS and achieves 64 dB dynamic range in 1MHz signal bandwidth. Second, an ultra-high performance oscillator-based delta-sigma modulator architecture is investigated. The proposed circuit is a third-order continuous-time PLL-Based Delta-Sigma Modulator with simulated 77 dB SNDR in 40MHz signal bandwidth with OSR of 16, and is fabricated in 65nm CMOS

Digital Intensive Mixed Signal Circuits with In-situ Performance Monitors

University of Minnesota Ph.D. dissertation.November 2016. Major: Electrical/Computer Engineering. Advisor: Chris Kim. 1 computer file (PDF); x, 137 pages.Digital intensive circuit design techniques of different mixed-signal systems such as data converters, clock generators, voltage regulators etc. are gaining attention for the implementation of modern microprocessors and system-on-chips (SoCs) in order to fully utilize the benefits of CMOS technology scaling. Moreover different performance improvement schemes, for example, noise reduction, spur cancellation, linearity improvement etc. can be easily performed in digital domain. In addition to that, increasing speed and complexity of modern SoCs necessitate the requirement of in-situ measurement schemes, primarily for high volume testing. In-situ measurements not only obviate the need for expensive measurement equipments and probing techniques, but also reduce the test time significantly when a large number of chips are required to be tested. Several digital intensive circuit design techniques are proposed in this dissertation along with different in-situ performance monitors for a variety of mixed signal systems. First, a novel beat frequency quantization technique is proposed in a two-step VCO quantizer based ADC implementation for direct digital conversion of low amplitude bio- potential signals. By direct conversion, it alleviates the requirement of the area and power consuming analog-frontend (AFE) used in a conventional ADC designs. This prototype design is realized in a 65nm CMOS technology. Measured SNDR is 44.5dB from a 10mVpp, 300Hz signal and power consumption is only 38μW. Next, three different clock generation circuits, a phase-locked loop (PLL), a multiplying delay-locked loop (MDLL) and a frequency-locked loop (FLL) are presented. First a 0.4-to-1.6GHz sub-sampling fractional-N all digital PLL architecture is discussed that utilizes a D-flip-flop as a digital sub-sampler. Measurement results from a 65nm CMOS test-chip shows 5dB lower phase noise at 100KHz offset frequency, compared to a conventional architecture. The Digital PLL (DPLL) architecture is further extended for a digital MDLL implementation in order to suppress the VCO phase noise beyond the DPLL bandwidth. A zero-offset aperture phase detector (APD) and a digital- to-time converter (DTC) are employed for static phase-offset (SPO) cancellation. A unique in-situ detection circuitry achieves a high resolution SPO measurement in time domain. A 65nm test-chip shows 0.2-to-1.45GHz output frequency range while reducing the phase-noise by 9dB compared to a DPLL. Next, a frequency-to-current converter (FTC) based fractional FLL is proposed for a low accuracy clock generation in an extremely low area for IoT application. High density deep-trench capacitors are used for area reduction. The test-chip is fabricated in a 32nm SOI technology that takes only 0.0054mm2 active area. A high-resolution in-situ period jitter measurement block is also incorporated in this design. Finally, a time based digital low dropout (DLDO) regulator architecture is proposed for fine grain power delivery over a wide load current dynamic range and input/output voltage in order to facilitate dynamic voltage and frequency scaling (DVFS). High- resolution beat frequency detector dynamically adjusts the loop sampling frequency for ripple and settling time reduction due to load transients. A fixed steady-state voltage offset provides inherent active voltage positioning (AVP) for ripple reduction. Circuit simulations in a 65nm technology show more than 90% current efficiency for 100X load current variation, while it can operate for an input voltage range of 0.6V – 1.2V

Architectural Alternatives to Implement High-Performance Delta-Sigma Modulators

RÉSUMÉ Le besoin d’appareils portatifs, de téléphones intelligents et de systèmes microélectroniques implantables médicaux s’accroît remarquablement. Cependant, l’optimisation de l’alimentation de tous ces appareils électroniques portables est l’un des principaux défis en raison du manque de piles à grande capacité utilisées pour les alimenter. C’est un fait bien établi que le convertisseur analogique-numérique (CAN) est l’un des blocs les plus critiques de ces appareils et qu’il doit convertir efficacement les signaux analogiques au monde numérique pour effectuer un post-traitement tel que l’extraction de caractéristiques. Parmi les différents types de CAN, les modulateurs Delta Sigma (��M) ont été utilisés dans ces appareils en raison des fonctionnalités alléchantes qu’ils offrent. En raison du suréchantillonnage et pour éloigner le bruit de la bande d’intérêt, un CAN haute résolution peut être obtenu avec les architectures ��. Il offre également un compromis entre la fréquence d’échantillonnage et la résolution, tout en offrant une architecture programmable pour réaliser un CAN flexible. Ces CAN peuvent être implémentés avec des blocs analogiques de faible précision. De plus, ils peuvent être efficacement optimisés au niveau de l’architecture et circuits correspondants. Cette dernière caractéristique a été une motivation pour proposer différentes architectures au fil des ans. Cette thèse contribue à ce sujet en explorant de nouvelles architectures pour optimiser la structure ��M en termes de résolution, de consommation d’énergie et de surface de silicium. Des soucis particuliers doivent également être pris en compte pour faciliter la mise en œuvre du ��M. D’autre part, les nouveaux procédés CMOS de conception et fabrication apportent des améliorations remarquables en termes de vitesse, de taille et de consommation d’énergie lors de la mise en œuvre de circuits numériques. Une telle mise à l’échelle agressive des procédés, rend la conception de blocs analogiques tel que un amplificateur de transconductance opérationnel (OTA), difficile. Par conséquent, des soins spéciaux sont également pris en compte dans cette thèse pour surmonter les problèmes énumérés. Ayant mentionné ci-dessus que cette thèse est principalement composée de deux parties principales. La première concerne les nouvelles architectures implémentées en mode de tension et la seconde partie contient une nouvelle architecture réalisée en mode hybride tension et temps.----------ABSTRACT The need for hand-held devices, smart-phones and medical implantable microelectronic sys-tems, is remarkably growing up. However, keeping all these electronic devices power optimized is one of the main challenges due to the lack of long life-time batteries utilized to power them up. It is a well-established fact that analog-to-digital converter (ADC) is one of the most critical building blocks of such devices and it needs to efficiently convert analog signals to the digital world to perform post processing such as channelizing, feature extraction, etc. Among various type of ADCs, Delta Sigma Modulators (��Ms) have been widely used in those devices due to the tempting features they offer. In fact, due to oversampling and noise-shaping technique a high-resolution ADC can be achieved with �� architectures. It also offers a compromise between sampling frequency and resolution while providing a highly-programmable approach to realize an ADC. Moreover, such ADCs can be implemented with low-precision analog blocks. Last but not the least, they are capable of being effectively power optimized at both architectural and circuit levels. The latter has been a motivation to proposed different architectures over the years.This thesis contributes to this topic by exploring new architectures to effectively optimize the ��M structure in terms of resolution, power consumption and chip area. Special cares must also be taken into account to ease the implementation of the ��M. On the other hand, advanced node CMOS processes bring remarkable improvements in terms of speed, size and power consumption while implementing digital circuits. Such an aggressive process scaling, however, make the design of analog blocks, e.g. operational transconductance amplifiers (OTAs), cumbersome. Therefore, special cares are also taken into account in this thesis to overcome the mentioned issues. Having had above mentioned discussion, this thesis is mainly split in two main categories. First category addresses new architectures implemented in a pure voltage domain and the second category contains new architecture realized in a hybrid voltage and time domain. In doing so, the thesis first focuses on a switched-capacitor implementation of a ��M while presenting an architectural solution to overcome the limitations of the previous approaches. This limitations include a power hungry adder in a conventional feed-forward topology as well as power hungry OTAs

Power-Efficient Design Techniques and Architectures for Scalable Submicron Analog Circuits

As the CMOS process scales down to submicron, digital circuit performance improves, while reduced supply voltage and lower transistor intrinsic gain make it difficult to implement analog circuits in a power efficient manner. Therefore, it has become advantageous to shift more analog signal processing functions conventionally realized in voltage (analog) domain into utilizing charge or time as the variable that can be processed by mostly digital/passive circuits. In this thesis, both circuit-level techniques and architectures are proposed that are inherently compatible with transistor scaling in submicron CMOS, meanwhile achieving state-of-the-art performance and optimizing power efficiency. The first part focuses on a highly reconfigurable charge-domain switched-g[subscript m]-C biquad band-pass filter (BPF) topology that utilizes an interleaved semi-passive charge sharing technique. It uses only switches, capacitors, linearity-enhanced gm-stages and digital circuitry for a 3-phase non-overlapping clock scheme. Flexible tunability in both center frequency and -3dB bandwidth is achieved with a scaling-compatible implementation. A 4th-order BPF prototype operating at a 1.2GS/s sampling rate is designed with a cascade of two proposed biquads in a 65nm LPE CMOS process. A tunable center frequency of 35−70MHz is measured with programmable bandwidth and a maximum stop-band rejection of 72dB. The measured in-band IIP3 is +12.5dBm. The filter prototype consumes 7.5mW total power from a 1.2V supply voltage, and occupies a core area of 0.17mm². In the second part, a highly linear continuous-time low-pass filter (LPF) topology with source follower coupling is presented that achieves excellent power efficiency. It synthesizes a 3rd-order low-pass transfer function in a single stage using coupled source followers and three capacitors, and can be configured to 2nd-order by disconnecting a capacitor. A 5th-order Butterworth prototype is designed with a cascade of two proposed filter stages in a 0.18μm CMOS, and occupies a core area of 0.12mm². Operating with a 1.3V supply voltage, the filter consumes only 0.5mA current, and achieves a -3dB bandwidth of 20MHz with 82dB stop-band rejection. A total harmonic distortion (THD) of -39.5dB at the output is measured with a +6.6dBm (i.e. 1.35V[subscript pk-pk]) input signal at 2MHz. The measured in-band IIP3 is +28.8dBm. The dynamic range (at 1% THD) is 76.8dB, with 15.3nV/√Hz averaged in-band input-referred noise. A pseudo-differential-VCO based 2nd-order continuous-time ΔΣ ADC with a residue self-coupling technique is proposed and implemented with mostly digital circuits in the third part. Two VCOs are arranged in a pseudo-differential manner. The digital output is obtained by comparing the sampled output phase of one VCO with that of the other. Passive subtraction is realized in current domain to obtain the residue at the VCO input. The residue self-coupling is implemented using a linear 1st-order transconductance low-pass filter (TCLPF). Moreover, a highly linear VCO topology is presented. The transistor-level simulations in a 65nm CMOS process show a 78dB SNDR over a 10MHz signal bandwidth with a power consumption of 2.9mW, which is 16dB improvement in contrast to the case with the TCLPF block powered off

Voltage and Time-Domain Analog Circuit Techniques for Scaled CMOS Technologies

CMOS technology scaling has resulted in reduced supply voltage and intrinsic voltage gain of the transistor. This presents challenges to the analog circuit designers due to lower signal swing and achievable signal to noise ratio (SNR), leading to increased power consumption. At the same time, device speed has increased in lower design nodes, which has not been directly beneficial for analog circuit design. This thesis presents voltage-domain and time-domain circuit scaling friendly circuit architectures that minimize the power consumption and benefit from the increasing transistor speeds. In the voltage-domain, an on-the-fly gain selection block is demonstrated as an alternative to the traditional MDAC architecture to enhance the input dynamic range of a medium-resolution medium-speed analog-to-digital converter (ADC) at reduced supply voltages. The proposed design also eliminates the need for a reference buffer, thus providing power savings. The measured prototype enhances the input dynamic range of a 12bit, 40MSPS ADC to 80.6dB at 1.2V supply voltage. In the time-domain, a generic circuit design approach is presented, followed by an in-depth analysis of Voltage-Controlled-Oscillator based Operational Transconductance Amplifiers (VCO-OTAs). A discrete-time-domain small-signal model based on the zero crossings of the internal VCOs is developed to predict the stability, the step response, and the frequency response of the circuit when placed in feedback. The model accurately predicts the circuit behavior for an arbitrary input frequency, even as the VCO free-running frequency approaches the unity-gain bandwidth of the closed-loop system, where other intuitive small-signal models available in the literature fail. Next, we present an application of VCO-OTA in designing a baseband trans-impedance amplifier (TIA) for current-mode receivers as a scaling-friendly and power-efficient alternative to the inverter-based OTA. We illustrate a design methodology for the choice of the VCO-OTA parameters in the context of a receiver design with an example of a 20MHz RF-channel-bandwidth receiver operating at 2GHz. Receiver simulation results demonstrate an improvement of up to 12dB in blocker 1dB compression point (B1dB) for slightly higher power consumption or up to 2.6x power reduction of the TIA resulting in up to 2x power reduction of the receiver for similar B1dB performance. Next, we present some examples of VCO-OTAs. We first illustrate the benefit of a VCO-OTA in a low-dropout-voltage regulator to achieve a dropout voltage of only100mV and operating down to 0.8V input supply, compared to the prototype based on traditional OTA with a minimum dropout voltage of 150mV, operating at a minimum of 1.2V supply. Both the capacitor-less prototypes can drive up to 1nF load capacitor and provide a current of 60mA. The next prototype showcases a method to reduce the power consumption of a VCO-OTA and spurs at the VCO frequency, with an application in the design of a fourth-order Butterworth filter at 4MHz. The thesis concludes with a design example of 0.2V VCO-OTA