High-Performance Design of a 4-Bit Carry Look-Ahead Adder in Static CMOS Logic

Design of a 4-bit Carry Look-Ahead (CLA) process in static CMOS logic has been presented. CLA architecture proposed in this work computes carry-out terms without using carry-propagate and carry-generate signals which are used in conventional static CMOS (C-CMOS) 4-bit CLA adder. Performance parameters of the proposed 4-bit CLA architecture have been simulated and validated by comparing with the conventional design using Cadence design toolset in 45 nm technology. The designs were compared in terms of average power consumption, propagation delay and power delay product (PDP). The proposed 4-bit CLA topology obtained 34.53 % improvement in speed, 4.84 % improvement in power consumption and 37.696 % improvement in PDP while the source voltage was 1.0 V. Hence, as per acquired simulation results, the proposed 4-bit CLA structure is proven to be an excellent alternative to the conventional design for data-path design in modern high-performance processors.Design of a 4-bit Carry Look-Ahead (CLA) process in static CMOS logic has been presented. CLA architecture proposed in this work computes carry-out terms without using carry-propagate and carry-generate signals which are used in conventional static CMOS (C-CMOS) 4-bit CLA adder. Performance parameters of the proposed 4-bit CLA architecture has been simulated and validated by comparing with the conventional design using Cadence design toolset in 45 nm technology. The designs were compared in terms of average power consumption, propagation delay and power delay product (PDP). The proposed 4-bit CLA topology obtained 26.67 % improvement in speed, 5.966 % improvement in power consumption and 31.06 % improvement in PDP while the source voltage was 1.0 V. Hence, as per acquired simulation results, the proposed 4-bit CLA structure is proven to be an excellent alternative to the conventional design for data-path design in modern high-performance processors

Design, upgrade and characterization of the silicon photomultiplier front-end for the AMIGA detector at the Pierre Auger Observatory

The successful installation, commissioning, and operation of the Pierre Auger Observatory would not have been possible without the strong commitment and effort from the technical and administrative staff in Malargue. We are very grateful to the following agencies and organizations for financial support: Argentina -Comision Nacional de Energia Atomica; Agencia Nacional de Promocion Cientifica y Tecnologica (ANPCyT); Consejo Nacional de Investigaciones Cientificas y Tecnicas (CONICET); Gobierno de la Provincia de Mendoza; Municipalidad de Malargue; NDM Holdings and Valle Las Lenas; in gratitude for their continuing cooperation over land access; Australia -the Australian Research Council; Brazil -Conselho Nacional de Desenvolvimento Cientifico e Tecnologico (CNPq); Financiadora de Estudos e Projetos (FINEP); Fundacao de Amparo a Pesquisa do Estado de Rio de Janeiro (FAPERJ); Sao Paulo Research Foundation (FAPESP) Grants No. 2019/10151-2, No. 2010/07359-6 and No. 1999/05404-3; Ministerio da Ciencia, Tecnologia, Inovacoes e Comunicacoes (MCTIC); Czech Republic Grant No. MSMT CR LTT18004, LM2015038, LM2018102, CZ.02.1.01/0.0/0.0/16_013/0001402, CZ.02.1.01/0.0/0.0/18_046/0016010 and CZ.02.1.01/0.0/0.0/17_049/0008422; France -Centre de Calcul IN2P3/CNRS; Centre National de la Recherche Scientifique (CNRS); Conseil Regional Ile-de-France; Departement Physique Nucleaire et Corpusculaire (PNC-IN2P3/CNRS); Departement Sciences de l'Univers (SDU-INSU/CNRS); Institut Lagrange de Paris (ILP) Grant No. LABEX ANR-10-LABX-63 within the Investissements d'Avenir Programme Grant No. ANR-11-IDEX-0004-02; Germany-Bundesministerium fur Bildung und Forschung (BMBF); Deutsche Forschungsgemeinschaft (DFG); Finanzministerium Baden-Wurttemberg; Helmholtz Alliance for Astroparticle Physics (HAP); Helmholtz-Gemeinschaft Deutscher Forschungszentren (HGF); Ministerium fur Innovation, Wissenschaft und Forschung des Landes Nordrhein-Westfalen; Ministerium fur Wissenschaft, Forschung und Kunst des Landes Baden-Wurttemberg; Italy-Istituto Nazionale di Fisica Nucleare (INFN); Istituto Nazionale di Astrofisica (INAF); Ministero dell'Istruzione, dell'Universita e della Ricerca (MIUR); CETEMPS Center of Excellence; Ministero degli Affari Esteri (MAE); Mexico-Consejo Nacional de Ciencia y Tecnologia (CONACYT) No. 167733; Universidad Nacional Autonoma de Mexico (UNAM); PAPIIT DGAPA-UNAM; The Netherlands -Ministry of Education, Culture and Science; Netherlands Organisation for Scientific Research (NWO); Dutch national e-infrastructure with the support of SURF Cooperative; Poland-Ministry of Science and Higher Education, grant No. DIR/WK/2018/11; National Science Centre, Grants No. 2013/08/M/ST9/00322, No. 2016/23/B/ST9/01635 and No. HARMONIA 5-2013/10/M/ST9/00062, UMO-2016/22/M/ST9/00198; Portugal -Portuguese national funds and FEDER funds within Programa Operacional Factores de Competitividade through Fundacao para a Ciencia e a Tecnologia (COMPETE); Romania-Romanian Ministry of Education and Research, the Program Nucleu within MCI(PN19150201/16N/2019 and PN19060102) and project PN-III-P1-1.2-PCCDI-2017-0839/19PCCDI/2018 within PNCDI III; Slovenia -Slovenian Research Agency, grants P1-0031, P1-0385, I0-0033, N1-0111; Spain-Ministerio de Economia, Industria y Competitividad (FPA2017-85114-P and FPA2017-85197-P), Xunta de Galicia (ED431C 2017/07), Junta de Andalucia (SOMM17/6104/UGR), Feder Funds, RENATA Red Nacional Tematica de Astroparticulas (FPA2015-68783-REDT) and Maria de Maeztu Unit of Excellence (MDM-2016-0692); U.S.A. -Department of Energy, Contracts No. DE-AC02-07CH11359, No. DE-FR02-04ER41300, No. DE-FG02-99ER41107 and No. DE-SC0011689; National Science Foundation, Grant No. 0450696; The Grainger Foundation; Marie Curie-IRSES/EPLANET; European Particle Physics Latin American Network; and UNESCO.AMIGA (Auger Muons and Infill for the Ground Array) is an upgrade of the Pierre Auger Observatory to complement the study of ultra-high-energy cosmic rays (UHECR) by measuring the muon content of extensive air showers (EAS). It consists of an array of 61 water Cherenkov detectors on a denser spacing in combination with underground scintillation detectors used for muon density measurement. Each detector is composed of three scintillation modules, with 10 m(2) detection area per module, buried at 2.3 m depth, resulting in a total detection area of 30 m(2). Silicon photomultiplier sensors (SiPM) measure the amount of scintillation light generated by charged particles traversing the modules. In this paper, the design of the front-end electronics to process the signals of those SiPMs and test results from the laboratory and from the Pierre Auger Observatory are described. Compared to our previous prototype, the new electronics shows a higher performance, higher efficiency and lower power consumption, and it has a new acquisition system with increased dynamic range that allows measurements closer to the shower core. The new acquisition system is based on the measurement of the total charge signal that the muonic component of the cosmic ray shower generates in the detector.Argentina - Comision Nacional de Energia AtomicaArgentina - Agencia Nacional de Promocion Cientifica y Tecnologica (ANPCyT)Argentina - Consejo Nacional de Investigaciones Cientificas y Tecnicas (CONICET)Argentina - Gobierno de la Provincia de MendozaArgentina - Municipalidad de MalargueArgentina - NDM HoldingsArgentina - Valle Las LenasAustralian Research CouncilConselho Nacional de Desenvolvimento Cientifico e Tecnologico (CNPQ) Fundacao de Apoio a Pesquisa do Distrito Federal (FAPDF) Brazil - Financiadora de Estudos e Projetos (FINEP)Fundacao Carlos Chagas Filho de Amparo a Pesquisa do Estado do Rio De Janeiro (FAPERJ)Fundacao de Amparo a Pesquisa do Estado de Sao Paulo (FAPESP) 2019/10151-2 2010/07359-6 1999/05404-3Brazil - Ministerio da Ciencia, Tecnologia, Inovacoes e Comunicacoes (MCTIC)Brazil - Czech Republic Grant MSMT CR LTT18004 LM2015038 LM2018102 CZ.02.1.01/0.0/0.0/16_013/0001402 CZ.02.1.01/0.0/0.0/18_046/0016010 CZ.02.1.01/0.0/0.0/17_049/0008422France - Centre de Calcul IN2P3/CNRSCentre National de la Recherche Scientifique (CNRS)France - Conseil Regional Ile-de-FranceFrance - Departement Physique Nucleaire et Corpusculaire (PNC-IN2P3/CNRS)France - Departement Sciences de l'Univers (SDU-INSU/CNRS)French National Research Agency (ANR) LABEX ANR-10-LABX-63Institut Lagrange de Paris (ILP) within the Investissements d'Avenir Programme ANR-11-IDEX-0004-02Federal Ministry of Education & Research (BMBF)Bundesministerium fur Bildung und Forschung (BMBF)German Research Foundation (DFG)Germany - Finanzministerium Baden-WurttembergGermany - Helmholtz Alliance for Astroparticle Physics (HAP)Germany - Helmholtz-Gemeinschaft Deutscher Forschungszentren (HGF)Germany - Ministerium fur Innovation, Wissenschaft und Forschung des Landes Nordrhein-WestfalenGermany - Ministerium fur Wissenschaft, Forschung und Kunst des Landes Baden-WurttembergItaly - Istituto Nazionale di Fisica Nucleare (INFN)Italy - Istituto Nazionale di Astrofisica (INAF)Italy - Ministero dell'Istruzione, dell'Universita e della Ricerca (MIUR)Italy - CETEMPS Center of ExcellenceConsejo Nacional de Ciencia y Tecnologia (CONACyT) 167733Mexico - Universidad Nacional Autonoma de Mexico (UNAM)Mexico - PAPIIT DGAPA-UNAMNetherlands - Ministry of Education, Culture and ScienceNetherlands Organization for Scientific Research (NWO)Netherlands Organisation for Scientific Research (NWO)The Netherlands - SURF CooperativePoland - Ministry of Science and Higher Education DIR/WK/2018/11 Poland - National Science Centre 2013/08/M/ST9/00322 2016/23/B/ST9/01635 HARMONIA 5-2013/10/M/ST9/00062 UMO-2016/22/M/ST9/00198Portugal - Portuguese national funds Portugal - FEDER funds within Programa Operacional Factores de Competitividade through Fundacao para a Ciencia e a Tecnologia (COMPETE)Romania - Romanian Ministry of Education and Research Romania - Program Nucleu within MCI PN19150201/16N/2019 PN19060102 Romania - PNCDI III PN-III-P1-1.2-PCCDI-2017-0839/19PCCDI/2018Slovenian Research Agency - Slovenia P1-0031 P1-0385 I0-0033 N1-0111Spain - Ministerio de Economia, Industria y Competitividad FPA2017-85114-P FPA2017-85197-PSpain - Xunta de Galicia ED431C 2017/07Junta de Andalucia SOMM17/6104/UGRSpain - Feder FundsSpain - RENATA Red Nacional Tematica de Astroparticulas FPA2015-68783-REDTSpain - Maria de Maeztu Unit of Excellence MDM-2016-0692United States Department of Energy (DOE) DE-AC02-07CH11359National Science Foundation (NSF) 0450696U.S.A. - Grainger Foundation U.S.A. - Marie Curie-IRSES/EPLANET U.S.A. - European Particle Physics Latin American Network U.S.A. - UNESCOItaly - Ministero degli Affari Esteri (MAE)The Netherlands - Dutch national e-infrastructur

Design, upgrade and characterization of the silicon photomultiplier front-end for the AMIGA detector at the Pierre Auger Observatory

AMIGA (Auger Muons and Infill for the Ground Array) is an upgrade of the Pierre Auger Observatory to complement the study of ultra-high-energy cosmic rays (UHECR) by measuring the muon content of extensive air showers (EAS). It consists of an array of 61 water Cherenkov detectors on a denser spacing in combination with underground scintillation detectors used for muon density measurement. Each detector is composed of three scintillation modules, with 10 m$^2$ detection area per module, buried at 2.3 m depth, resulting in a total detection area of 30 m$^2$. Silicon photomultiplier sensors (SiPM) measure the amount of scintillation light generated by charged particles traversing the modules. In this paper, the design of the front-end electronics to process the signals of those SiPMs and test results from the laboratory and from the Pierre Auger Observatory are described. Compared to our previous prototype, the new electronics shows a higher performance, higher efficiency and lower power consumption, and it has a new acquisition system with increased dynamic range that allows measurements closer to the shower core. The new acquisition system is based on the measurement of the total charge signal that the muonic component of the cosmic ray shower generates in the detector.Comment: 40 pages, 33 figure

Optical code-division multiple access system and optical signal processing

This thesis presents our recent researches on the development of coding devices, the investigation of security and the design of systems in the optical cod-division multiple access (OCDMA) systems. Besides, the techniques of nonlinear signal processing used in the OCDMA systems fire our imagination, thus some researches on all-optical signal processing are carried out and also summarized in this thesis. Two fiber Bragg grating (FBG) based coding devices are proposed. The first coding device is a superstructured FBG (SSFBG) using ±π/2-phase shifts instead of conventional 0/π-phase shifts. The ±π/2-phase-shifted SSFBG en/decoders can not only conceal optical codes well in the encoded signals but also realize the reutilization of available codes by hybrid use with conventional 0/π-phase-shifted SSFBG en/decoders. The second FBG based coding device is synthesized by layer-peeling method, which can be used for simultaneous optical code recognition and chromatic dispersion compensation. Then, two eavesdropping schemes, one-bit delay interference detection and differential detection, are demonstrated to reveal the security vulnerability of differential phase-shift keying (DPSK) and code-shift keying (CSK) OCDMA systems. To address the security issue as well as increase the transmission capacity, an orthogonal modulation format based on DPSK and CSK is introduced into the OCDMA systems. A 2 bit/symbol 10 Gsymbol/s transmission system using the orthogonal modulation format is achieved. The security of the system can be partially guaranteed. Furthermore, a fully-asynchronous gigabit-symmetric OCDMA passive optical network (PON) is proposed, in which a self-clocked time gate is employed for signal regeneration. A remodulation scheme is used in the PON, which let downstream and upstream share the same optical carrier, allowing optical network units source-free. An error-free 4-user 10 Gbit/s/user duplex transmission over 50 km distance is reazlied. A versatile waveform generation scheme is then studied. A theoretical model is established and a waveform prediction algorithm is summarized. In the demonstration, various waveforms are generated including short pulse, trapezoidal, triangular and sawtooth waveforms and doublet pulse. ii In addition, an all-optical simultaneous half-addition and half-subtraction scheme is achieved at an operating rate of 10 GHz by using only two semiconductor optical amplifiers (SOA) without any assist light. Lastly, two modulation format conversion schemes are demonstrated. The first conversion is from NRZ-OOK to PSK-Manchester coding format using a SOA based Mach-Zehnder interferometer. The second conversion is from RZ-DQPSK to RZ-OOK by employing a supercontinuum based optical thresholder

Doctor of Philosophy

dissertationAsynchronous design has a very promising potential even though it has largely received a cold reception from industry. Part of this reluctance has been due to the necessity of custom design languages and computer aided design (CAD) flows to design, optimize, and validate asynchronous modules and systems. Next generation asynchronous flows should support modern programming languages (e.g., Verilog) and application specific integrated circuits (ASIC) CAD tools. They also have to support multifrequency designs with mixed synchronous (clocked) and asynchronous (unclocked) designs. This work presents a novel relative timing (RT) based methodology for generating multifrequency designs using synchronous CAD tools and flows. Synchronous CAD tools must be constrained for them to work with asynchronous circuits. Identification of these constraints and characterization flow to automatically derive the constraints is presented. The effect of the constraints on the designs and the way they are handled by the synchronous CAD tools are analyzed and reported in this work. The automation of the generation of asynchronous design templates and also the constraint generation is an important problem. Algorithms for automation of reset addition to asynchronous circuits and power and/or performance optimizations applied to the circuits using logical effort are explored thus filling an important hole in the automation flow. Constraints representing cyclic asynchronous circuits as directed acyclic graphs (DAGs) to the CAD tools is necessary for applying synchronous CAD optimizations like sizing, path delay optimizations and also using static timing analysis (STA) on these circuits. A thorough investigation for the requirements of cycle cutting while preserving timing paths is presented with an algorithm to automate the process of generating them. A large set of designs for 4 phase handshake protocol circuit implementations with early and late data validity are characterized for area, power and performance. Benchmark circuits with automated scripts to generate various configurations for better understanding of the designs are proposed and analyzed. Extension to the methodology like addition of scan insertion using automatic test pattern generation (ATPG) tools to add testability of datapath in bundled data asynchronous circuit implementations and timing closure approaches are also described. Energy, area, and performance of purely asynchronous circuits and circuits with mixed synchronous and asynchronous blocks are explored. Results indicate the benefits that can be derived by generating circuits with asynchronous components using this methodology

Enhanced Hardware Security Using Charge-Based Emerging Device Technology

The emergence of hardware Trojans has largely reshaped the traditional view that the hardware layer can be blindly trusted. Hardware Trojans, which are often in the form of maliciously inserted circuitry, may impact the original design by data leakage or circuit malfunction. Hardware counterfeiting and IP piracy are another two serious issues costing the US economy more than $200 billion annually. A large amount of research and experimentation has been carried out on the design of these primitives based on the currently prevailing CMOS technology. However, the security provided by these primitives comes at the cost of large overheads mostly in terms of area and power consumption. The development of emerging technologies provides hardware security researchers with opportunities to utilize some of the otherwise unusable properties of emerging technologies in security applications. In this dissertation, we will include the security consideration in the overall performance measurements to fully compare the emerging devices with CMOS technology. The first approach is to leverage two emerging devices (Silicon NanoWire and Graphene SymFET) for hardware security applications. Experimental results indicate that emerging device based solutions can provide high level circuit protection with relatively lower performance overhead compared to conventional CMOS counterpart. The second topic is to construct an energy-efficient DPA-resilient block cipher with ultra low-power Tunnel FET. Current-mode logic is adopted as a circuit-level solution to countermeasure differential power analysis attack, which is mostly used in the cryptographic system. The third investigation targets on potential security vulnerability of foundry insider\u27s attack. Split manufacturing is adopted for the protection on radio-frequency (RF) circuit design

Digital Background Self-Calibration Technique for Compensating Transition Offsets in Reference-less Flash ADCs

This Dissertation focusses on proving that background calibration using adaptive algorithms are low-cost, stable and effective methods for obtaining high accuracy in flash A/D converters. An integrated reference-less 3-bit flash ADC circuit has been successfully designed and taped out in UMC 180 nm CMOS technology in order to prove the efficiency of our proposed background calibration. References for ADC transitions have been virtually implemented built-in in the comparators dynamic-latch topology by a controlled mismatch added to each comparator input front-end. An external very simple DAC block (calibration bank) allows control the quantity of mismatch added in each comparator front-end and, therefore, compensate the offset of its effective transition with respect to the nominal value. In order to assist to the estimation of the offset of the prototype comparators, an auxiliary A/D converter with higher resolution and lower conversion speed than the flash ADC is used: a 6-bit capacitive-DAC SAR type. Special care in synchronization of analogue sampling instant in both ADCs has been taken into account. In this thesis, a criterion to identify the optimum parameters of the flash ADC design with adaptive background calibration has been set. With this criterion, the best choice for dynamic latch architecture, calibration bank resolution and flash ADC resolution are selected. The performance of the calibration algorithm have been tested, providing great programmability to the digital processor that implements the algorithm, allowing to choose the algorithm limits, accuracy and quantization errors in the arithmetic. Further, systematic controlled offset can be forced in the comparators of the flash ADC in order to have a more exhaustive test of calibration