Ring Amplifiers for Switched Capacitor Circuits

In this paper the fundamental concept of ring amplification is introduced and explored. Ring amplifiers enable efficient amplification in scaled environments, and possess the benefits of efficient slew-based charging, rapid stabilization, compression-immunity (inherent rail-to-rail output swing), and performance that scales with process technology. A basic operational theory is established, and the core benefits of this technique are identified. Measured results from two separate ring amplifier based pipelined ADCs are presented. The first prototype IC, a simple 10.5-bit, 61.5dB SNDR pipelined ADC which uses only ring amplifiers, is used to demonstrate the core benefits. The second fabricated IC presented is a high-resolution pipelined ADC which employs the technique of Split-CLS to perform efficient, accurate amplification aided by ring amplifiers. The 15-bit ADC is implemented in a 0.18 μm CMOS technology and achieves 76.8 dB SNDR and 95.4 dB SFDR at 20 Msps while consuming 5.1 mW, achieving a FoM of 45 fJ/conversion-step.Keywords: correlated level shifting, analog to digital conversion, analog to digital converter, slew-based, RAMP, rail-to-rail, ring amplification, ADC, CLS, ringamp, A/D, low power, ring amp, scaling, Split-CLS, ring amplifier, high resolution, switched-capacitor, scalability, stabilized ring oscillator, nanoscale CMOSThis is the author's peer-reviewed final manuscript, as accepted by the publisher. The published article is copyrighted by IEEE-Institute of Electrical and Electronics Engineers and can be found at: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=4. ©2012 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other users, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works for resale or redistribution to servers or lists, or reuse of any copyrighted components of this work in other works

Energy Efficient Pipeline ADCs Using Ring Amplifiers

Pipeline ADCs require accurate amplification. Traditionally, an operational transconductance amplifier (OTA) configured as a switched-capacitor (SC) amplifier performs such amplification. However, traditional OTAs limit the power efficiency of ADCs since they require high quiescent current for slewing and bandwidth. In addition, it is difficult to design low-voltage OTAs in modern, scaled CMOS. The ring amplifier is an energy efficient and high output swing alternative to an OTA for SC circuits which is basically a three-stage inverter amplifier stabilized in a feedback configuration. However, the conventional ring amplifier requires external biases, which makes the ring amplifier less practical when we consider process, supply voltage, and temperature (PVT) variation. In this dissertation, three types of innovative ring amplifiers are presented and verified with state-of-the-art energy efficient pipeline ADCs. These new ring amplifiers overcome the limitations of the conventional ring amplifier and further improve energy efficiency. The first topic of this dissertation is a self-biased ring amplifier that makes the ring amplifier more practical and power efficient, while maintaining the benefits of efficient slew-based charging and an almost rail-to-rail output swing. In addition, the ring amplifiers are also used as comparators in the 1.5b sub-ADCs by utilizing the unique characteristics of the ring amplifier. This removes the need for dedicated comparators in sub-ADCs, thus further reducing the power consumption of the ADC. The prototype 10.5b 100 MS/s comparator-less pipeline ADC with the self-biased ring amplifiers has measured SNDR, SNR and SFDR of 56.6 dB (9.11b), 57.5 dB and 64.7 dB, respectively, and consumes 2.46 mW, which results in Walden Figure-of-Merit (FoM) of 46.1 fJ/ conversion∙step. The second topic is a fully-differential ring amplifier, which solves the problems of single-ended ring amplifiers while maintaining the benefits of the single-ended ring amplifiers. This differential ring-amplifier is applied in a 13b 50 MS/s SAR-assisted pipeline ADC. Furthermore, an improved capacitive DAC switching method for the first stage SAR reduces the DAC linearity errors and switching energy. The prototype ADC achieves measured SNDR, SNR and SFDR of 70.9 dB (11.5b), 71.3 dB and 84.6 dB, respectively, and consumes 1 mW. This measured performance is equivalent to Walden and Schreier FoMs of 6.9 fJ/conversion∙step and 174.9 dB, respectively. Finally, a four-stage fully-differential ring amplifier improves the small-signal gain to over 90 dB without compromising speed. In addition, a new auto-zero noise filtering method reduces noise without consuming additional power. This is more area efficient than the conventional auto-zero noise folding reduction technique. A systematic mismatch free SAR CDAC layout method is also presented. The prototype 15b 100 MS/s calibration-free SAR-assisted pipeline ADC using the four-stage ring amplifier achieves 73.2 dB SNDR (11.9b) and 90.4 dB SFDR with a 1.1 V supply. It consumes 2.3 mW resulting in Schreier FoM of 176.6 dB.PHDElectrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttps://deepblue.lib.umich.edu/bitstream/2027.42/138759/1/yonglim_1.pd

Ring amplification for switched capacitor circuits

A comprehensive and scalable solution for high-performance switched capacitor amplification is presented. Central to this discussion is the concept of ring amplification. A ring amplifier is a small modular amplifier derived from a ring oscillator that naturally embodies all the essential elements of scalability. It can amplify with accurate rail-to-rail output swing, drive large capacitive loads with extreme efficiency using slew-based charging, naturally scale in performance according to process trends, and is simple enough to be quickly constructed from only a handful of inverters, capacitors, and switches. In addition, the gain-enhancement technique of Split-CLS is introduced, and used to extend the efficacy of ring amplifiers in specific and other amplifiers in general. Four different pipelined ADC designs are presented which explore the practical implementation options and design considerations relevant to ring amplification and Split-CLS, and are used to establish ring amplification as a new paradigm for scalable amplification

Ring Amplifier Optimized for High Resolution Analog-to-Digital Converter Applications

In recent years, SAR ADCs have been shown to acheive faster conversion times and improved power efficiencies due to their simple building blocks that are digital in nature and scale favorably with technology. High resolution ADCs with stringent noise requirement has led to the adoption of hybrid ADC architectures such as the two-step SAR. The two-step SAR ADC, also known as pipelined SAR ADC, combine the concepts of SAR and Pipeline ADC architecture where a residue amplifier provides a critical amplification step. An amplifier architecture well suited for residue amplification known as Ring Amplifier (RAMP) has enabled power efficient two-step SAR ADCs. However, RAMP based ADCs with greater than 14 bits of resolution has not been attempted in previous literature. In this work, the design and measurement of a high-resolution two-step SAR ADC utilizing an enhanced RAMP is demonstrated. Additional circuit techniques are introduced that contribute to the energy-efficiency of the ADC. The ADC implemented in 0.18$\mu$m technology achieves a DR of 95dB and a Schreier FOM better than 180dB at both 2MS/s and 15MS/s

Reconfigurable low power robust pipeline ADC for Biomedical applications

Demand for high-performance analog-to-digital converter (ADC) integrated circuits (ICs) with optimal combined specifications of resolution, sampling rate and power consumption becomes dominant due to emerging applications in wireless communications, broad band transceivers, digital-intermediate frequency (IF) receivers and countless of digital devices. This research is dedicated to develop a pipeline ADC design methodology with minimum power dissipation, while keeping relatively high speed and high resolution

A Low-Power, Reconfigurable, Pipelined ADC with Automatic Adaptation for Implantable Bioimpedance Applications

Biomedical monitoring systems that observe various physiological parameters or electrochemical reactions typically cannot expect signals with fixed amplitude or frequency as signal properties can vary greatly even among similar biosignals. Furthermore, advancements in biomedical research have resulted in more elaborate biosignal monitoring schemes which allow the continuous acquisition of important patient information. Conventional ADCs with a fixed resolution and sampling rate are not able to adapt to signals with a wide range of variation. As a result, reconfigurable analog-to-digital converters (ADC) have become increasingly more attractive for implantable biosensor systems. These converters are able to change their operable resolution, sampling rate, or both in order convert changing signals with increased power efficiency. Traditionally, biomedical sensing applications were limited to low frequencies. Therefore, much of the research on ADCs for biomedical applications focused on minimizing power consumption with smaller bias currents resulting in low sampling rates. However, recently bioimpedance monitoring has become more popular because of its healthcare possibilities. Bioimpedance monitoring involves injecting an AC current into a biosample and measuring the corresponding voltage drop. The frequency of the injected current greatly affects the amplitude and phase of the voltage drop as biological tissue is comprised of resistive and capacitive elements. For this reason, a full spectrum of measurements from 100 Hz to 10-100 MHz is required to gain a full understanding of the impedance. For this type of implantable biomedical application, the typical low power, low sampling rate analog-to-digital converter is insufficient. A different optimization of power and performance must be achieved. Since SAR ADC power consumption scales heavily with sampling rate, the converters that sample fast enough to be attractive for bioimpedance monitoring do not have a figure-of-merit that is comparable to the slower converters. Therefore, an auto-adapting, reconfigurable pipelined analog-to-digital converter is proposed. The converter can operate with either 8 or 10 bits of resolution and with a sampling rate of 0.1 or 20 MS/s. Additionally, the resolution and sampling rate are automatically determined by the converter itself based on the input signal. This way, power efficiency is increased for input signals of varying frequency and amplitude

Design de Amplificadores Resíduo para Aplicações em ADCs Pipeline

Desenvolvimento de um amplificador resíduo para aplicações em conversores analógico digitais concorrenciais, baseando-se em técnicas como amplificação com realimentação positiva, amplificação paramétrica e montagem dreno-comum, tentando construir um amplificador dinâmico com tecnologia CMOS avançada de 130 nm. O objectivo deste amplificador é connseguir um ganho nominal entre 4x (V/V) e 8 (V/V). Utilizamos uma montagem seguidora de ganho aproximadamente 1, desprezando o efeito de corpo, conseguindo obter o ganho através da diferença entre os valores das capacidades entre as duas fases. Posteriormente ao dimensionamento, fazemos a análise de ganho, análise FFT e consumo. Obteu-se um ganho nominal de 4 e um amplificador que funciona num leque alargado de temperaturas [-40º, 140º] com um consumo bastante baixo - 92 uW -, a 10 Mhz.Development of a residual amplifier for applications in competitive digital analog converters, based on techniques such as positive feedback amplification, parametric amplification and common drain assembly, trying to build a dynamic amplifier with 130 nm advanced CMOS technology. The purpose of this amplifier is to achieve a nominal gain between 4x (V/V) and 8x (V/V). We used a follower assembly of approximately 1 gain, disregarding the body effect, managing to obtain the gain through the difference between the values of the capacities between the two phases. After dimensioning, we do the analysis of gain, FFT analysis and consumption. A nominal gain of 4 was obtained and an amplifier that operates in a wide range of temperatures [-40º, 140º] with a very low consumption - 92 uW -, at 10 Mhz

Mismatch-Immune Successive-Approximation Techniques for Nanometer CMOS ADCs

During the past decade, SAR ADCs have enjoyed increasing prominence due to their inherently scaling-friendly architecture. Several recent SAR ADC innovations focus on decreasing power consumption, mitigating thermal noise, and improving bandwidth, however most of those that use non-hybrid architectures are limited to moderate (8-10 bit) resolu- tion. Assuming an almost rail-to-rail dynamic range, comparator noise and DAC element mismatch constraints are critical but not insurmountable at 10 bits of resolution or less in sub-100nm processes. On the other hand, analysis shows that for medium-resolution ADCs (11-15 bits, depending on the LSB voltage of the converter), the mismatch sizing constraint still dominates unit capacitor sizing over the kT/C sampling noise constraint, and can only be mitigated by drawing increasingly larger capacitors. The focus of this work is to extend the scaling benefits of the SAR architecture to medium and higher ADC resolutions through mitigating and ultimately harnessing DAC element mismatch. This goal is achieved via a novel, completely reconfigurable capacitor DAC that allows the rearranging of capacitors to different trial groupings in the SAR cycle so that mismatch can be canceled. The DAC is implemented in a 12-bit SAR ADC in 65nm CMOS, and a nearly 2-bit improvement in linearity is demonstrated with a simple reconfiguration algorithm.PHDElectrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttps://deepblue.lib.umich.edu/bitstream/2027.42/138630/1/ncolins_1.pd