Power-efficient high-speed interface circuit techniques

Inter- and intra-chip connections have become the new challenge to enable the scaling of computing systems, ranging from mobile devices to high-end servers. Demand for aggregate I/O bandwidth has been driven by applications including high-speed ethernet, backplane micro-servers, memory, graphics, chip-to-chip and network onchip. I/O circuitry is becoming the major power consumer in SoC processors and memories as the increasing bandwidth demands larger per-pin data rate or larger I/O pin count per component. The aggregate I/O bandwidth has approximately doubled every three to four years across a diverse range of standards in different applications. However, in order to keep pace with these standards enabled in part by process-technology scaling, we will require more than just device scaling in the near future. New energy-efficient circuit techniques must be proposed to enable the next generations of handheld and high-performance computers, given the thermal and system-power limits they start facing. ^ In this work, we are proposing circuit architectures that improve energy efficiency without decreasing speed performance for the most power hungry circuits in high speed interfaces. By the introduction of a new kind of logic operators in CMOS, called implication operators, we implemented a new family of high-speed frequency dividers/prescalers with reduced footprint and power consumption. New techniques and circuits for clock distribution, for pre-emphasis and for driver at the transmitter side of the I/O circuitry have been proposed and implemented. At the receiver side, new DFE architecture and CDR have been proposed and have been proven experimentally

Architectures and Circuits Leveraging Injection-Locked Oscillators for Ultra-Low Voltage Clock Synthesis and Reference-less Receivers for Dense Chip-to-Chip Communications

High performance computing is critical for the needs of scientific discovery and economic competitiveness. An extreme-scale computing system at 1000x the performance of today’s petaflop machines will exhibit massive parallelism on multiple vertical fronts, from thousands of computational units on a single processor to thousands of processors in a single data center. To facilitate such a massively-parallel extreme-scale computing, a key challenge is power. The challenge is not power associated with base computation but rather the problem of transporting data from one chip to another at high enough rates. This thesis presents architectures and techniques to achieve low power and area footprint while achieving high data rates in a dense very-short reach (VSR) chip-to-chip (C2C) communication network. High-speed serial communication operating at ultra-low supplies improves the energy-efficiency and lowers the power envelop of a system doing an exaflop of loops. One focus area of this thesis is clock synthesis for such energy-efficient interconnect applications operating at high speeds and ultra-low supplies. A sub-integer clockfrequency synthesizer is presented that incorporates a multi-phase injection-locked ring-oscillator-based prescaler for operation at an ultra-low supply voltage of 0.5V, phase-switching based programmable division for sub-integer clock-frequency synthesis, and automatic calibration to ensure injection lock. A record speed of 9GHz has been demonstrated at 0.5V in 45nm SOI CMOS. It consumes 3.5mW of power at 9.12GHz and 0.052 of area, while showing an output phase noise of -100dBc/Hz at 1MHz offset and RMS jitter of 325fs; it achieves a net of -186.5 in a 45-nm SOI CMOS process. This thesis also describes a receiver with a reference-less clocking architecture for high-density VSR-C2C links. This architecture simplifies clock-tree planning in dense extreme-scaling computing environments and has high-bandwidth CDR to enable SSC for suppressing EMI and to mitigate TX jitter requirements. It features clock-less DFE and a high-bandwidth CDR based on master-slave ILOs for phase generation/rotation. The RX is implemented in 14nm CMOS and characterized at 19Gb/s. It is 1.5x faster that previous reference-less embedded-oscillator based designs with greater than 100MHz jitter tolerance bandwidth and recovers error-free data over VSR-C2C channels. It achieves a power-efficiency of 2.9pJ/b while recovering error-free data (BER 200MHz and the INL of the ILO-based phase-rotator (32- Steps/UI) is <1-LSB. Lastly, this thesis develops a time-domain delay-based modeling of injection locking to describe injection-locking phenomena in nonharmonic oscillators. The model is used to predict the locking bandwidth, and the locking dynamics of the locked oscillator. The model predictions are verified against simulations and measurements of a four-stage differential ring oscillator. The model is further used to predict the injection-locking behavior of a single-ended CMOS inverter based ring oscillator, the lock range of a multi-phase injection-locked ring-oscillator-based prescaler, as well as the dynamics of tracking injection phase perturbations in injection-locked masterslave oscillators; demonstrating its versatility in application to any nonharmonic oscillator

Quadrature Frequency Synthesis for Wideband Wireless Transceivers

University of Minnesota Ph.D. dissertation. May 2014. Major: Electrical Engineering. Advisor: Ramesh Harjani. 1 computer file (PDF); xi, 112 pages.In this thesis, three different techniques pertinent to quadrature LO generation in high data rate and wideband RF transceivers are presented. Prototype designs are made to verify the performance of the proposed techniques, in three different technologies: IBM 130nm CMOS process, TSMC 65nm CMOS process and IBM 32nm SOI process. The three prototype designs also cover three different frequency bands, ranging from 5GHz to 74GHz. First, an LO generation scheme for a 21 GHz center-frequency, 4-GHz instantaneous bandwidth channelized receiver is presented. A single 1.33 GHz reference source is used to simultaneously generate 20 GHz and 22 GHz LOs with quadrature outputs. Injection locking is used instead of conventional PLL techniques allowing low-power quadrature generation. A harmonic-rich signal, containing both even and odd harmonics of the input reference signal, is generated using a digital pulse slimmer. Two ILO chains are used to lock on to the 10th and 11th harmonics of the reference signal generating the 20 GHz and the 22 GHz quadrature LOs respectively. The prototype design is implemented in IBM's 130 nm CMOS process, draws 110 mA from a 1.2 V supply and occupies an active area of 1.8 square-mm. Next, a wide-tuning range QVCO with a novel complimentary-coupling technique is presented. By using PMOS transistors for coupling two VCOs with NMOS gm-cells, it is shown that significant phase-noise improvement (7-9 dB) can be achieved over the traditional NMOS coupling. This breaks the trade-off between quadrature accuracy and phase-noise, allowing reasonable accuracy without a significant phase-noise hit. The proposed technique is frequency-insensitive, allowing robust coupling over a wide tuning range. A prototype design is done in TSMC 65nm process, with 4-bits of discrete tuning spanning the frequency range 4.6-7.8 GHz (52% FTR) while achieving a minimum FOM of 181.4dBc/Hz and a minimum FOMT of 196dBc/Hz. Finally, a wide tuning-range millimeter wave QVCO is presented that employs a modified transformer-based super-harmonic coupling technique. Using the proposed technique, together with custom-designed inductors and metal capacitors, a prototype is designed in IBM 32nm SOI technology with 6-bits of discrete tuning using switched capacitors. Full EM-extracted simulations show a tuning range of 53.84GHz to 73.59GHz, with an FOM of 173 dBc/Hz and an FOMT of 183 dBc/Hz. With 19.75GHz of tuning range around a 63.7GHz center frequency, the simulated FTR is 31%, surpassing all similar designs in the same band. A slight modification in the tank inductors would enable the QVCO to be employed in multiple mm-Wave bands (57-66 GHz communication band, 71-76 GHz E-band, and 76-77 GHz radar band)

Analysis and design of an 80 Gbit/sec clock and data recovery prototype

La demande croissante de toujours plus de débit pour les télécommunications entraine une augmentation de la fréquence de fonctionnement des liaisons séries. Cette demande se retrouve aussi dans les systèmes embarqués du fait de l'augmentation des performances des composants et périphériques. Afin de s'assurer que le train de données est bien réceptionné, un circuit de restitution d'horloge et de données est placé avant tout traitement du coté du récepteur. Dans ce contexte, les activités de recherche présentées dans cette thèse se concentrent sur la conception d'une CDR (Clock and Data Recovery). Nous détaillerons le comparateur de phase qui joue un rôle critique dans un tel système. Cette thèse présente un comparateur de phase ayant comme avantage d'avoir une mode de fenêtrage et une fréquence de fonctionnement réduite. La topologie spéciale utilisée pour la CDR est décrite, et la théorie relative aux oscillateurs verrouillés en injection est expliquée. L'essentiel du travail de recherche s'est concentrée sur la conception et le layout d'une restitution d'horloge dans le domaine millimétrique, à 80 Gbps. Pour cela plusieurs prototypes ont été réalisés en technologie BiCMOS 130 nm de STMicrolectronics.The increasing bandwidth demand for telecommunication leads to an important rise of serial link operating frequencies. This demand is also present in embedded systems with the growth of devices and peripherals performances. To ensure the data stream is well recovered, a clock and data recovery (CDR) circuit is placed before any logical blocks on the receiver side. The research activities presented in this thesis are related to the design of such a CDR. The phase detector plays a critical role in the CDR circuit and is specially studied. This thesis presents a phase comparator that provides an enhancement by introducing a windowed mode and reducing its operating frequency. The used CDR has a special topology, which is described, and the injection locked oscillator theory is explained. Most of the research of this study has focused on the design and layout of a 80 Gbps CDR. Several prototypes are realized in 130 nm SiGe process from STMicroelectronics.BORDEAUX1-Bib.electronique (335229901) / SudocSudocFranceF

Conception et étude d’une synthèse de fréquence innovante en technologies CMOS avancées pour les applications en bande de fréquence millimétrique

The 60-GHz unlicensed band is a promising alternative to perform the high data rate required in the next generation of wireless communication systems. Complex modulations such as OFDM or 64-QAM allow reaching multi-gigabits per second throughput over up to several tens of meters in standard CMOS technologies. This performance rely on the use of high performance millimeter-wave frequency synthesizer in the RF front-end. In this work, an original architecture is proposed to generate this high performance millimeter-wave frequency synthesizer. It is based on a high order (several tens) multiplication of a low frequency reference (few GHz), that is capable of copying the low frequency reference spectral properties. This high order frequency multiplication is performed in two steps. Firstly, a multi-harmonic signal which power is located around the harmonic of interest is generated from the low frequency reference signal. Secondly, the harmonic of interest is filtered out from this multi-harmonic signal. Both steps rely on the specific use of oscillators. This work deals with the circuit design on advanced CMOS technologies (40 nm CMOS, 55 nm BiCMOS) for the proof of concept and on the theoretical study of this system. This novel technique is experimentally validated by measurements on the fabricated circuits and exhibit state-of-the-art performance. The analytical study of this high order frequency multiplication led to the discovery of a particular kind of synchronization in oscillators and to approximated solutions of the Van der Pol equation in two different practical cases. The perspectives of this work include the design of the low frequency reference and the integration of this frequency synthesizer in a complete RF front-end architecture.La bande de fréquence non-licensée autour de 60 GHz est une alternative prometteuse pour couvrir les besoins en bande passante des futurs systèmes de communication. L'utilisation de modulations complexes (comme OFDM ou 64-QAM) à ces fréquences permet d'atteindre, en utilisant une technologie CMOS standard, des débits de plusieurs gigabits par seconde sur quelques mètres voire quelques dizaines de mètres. Pour atteindre ces performances, la tête d'émission-réception RF (front-end RF) doit être dotée d'une référence de fréquence haute performance. Dans ce travail, une architecture originale est proposée pour générer cette référence de fréquence haute performance. Elle repose sur la multiplication de fréquence d'ordre élevé (plusieurs dizaines) d'un signal de référence basse fréquence (moins de quelques GHz), tout en recopiant les propriétés spectrales du signal basse fréquence. Cette multiplication est réalisée en combinant la production d'un signal multi-harmonique dont la puissance est concentrée autour de la fréquence à synthétiser. L'harmonique d'intérêt est ensuite extraite au moyen d'un filtrage. Ces deux étapes reposent sur l'utilisation d'oscillateurs dans des configurations spécifiques. Ce travail porte à la fois sur la mise en équation et l'étude du fonctionnement de ce système, et sur la conception de circuits dans des technologies CMOS avancées (CMOS 40 nm, BiCMOS 55 nm). Les mesures sur les circuits fabriqués permettent de valider la preuve de concept ainsi que de montrer des performances à l'état de l'art. L'étude du fonctionnement de ce système a conduit à la découverte d'une forme particulière de synchronisation des oscillateurs ainsi qu'à l'expression de solutions approchées de l'équation de Van der Pol dans deux cas pratiques particuliers. Les perspectives de ce travail sont notamment l'intégration de cette synthèse innovante dans un émetteur-récepteur complet