Study and implementation of a PVT insensitive CMOS oscillator

Fallières Armand. Circulaire adressée aux Préfets, au sujet du classement des instituteurs. In: Bulletin administratif de l'instruction publique. Tome 47 n°891, 1890. pp. 137-138

A Low-Power BFSK/OOK Transmitter for Wireless Sensors

In recent years, significant improvements in semiconductor technology have allowed consistent development of wireless chipsets in terms of functionality and form factor. This has opened up a broad range of applications for implantable wireless sensors and telemetry devices in multiple categories, such as military, industrial, and medical uses. The nature of these applications often requires the wireless sensors to be low-weight and energy-efficient to achieve long battery life. Among the various functions of these sensors, the communication block, used to transmit the gathered data, is typically the most power-hungry block. In typical wireless sensor networks, transmission range is below 10 meters and required radiated power is below 1 milliwatt. In such cases, power consumption of the frequency-synthesis circuits prior to the power amplifier of the transmitter becomes significant. Reducing this power consumption is currently the focus of various research endeavors. A popular method of achieving this goal is using a direct-modulation transmitter where the generated carrier is directly modulated with baseband data using simple modulation schemes. Among the different variations of direct-modulation transmitters, transmitters using unlocked digitally-controlled oscillators and transmitters with injection or resonator-locked oscillators are widely investigated because of their simple structure. These transmitters can achieve low-power and stable operation either with the help of recalibration or by sacrificing tuning capability. In contrast, phase-locked-loop-based (PLL) transmitters are less researched. The PLL uses a feedback loop to lock the carrier to a reference frequency with a programmable ratio and thus achieves good frequency stability and convenient tunability. This work focuses on PLL-based transmitters. The initial goal of this work is to reduce the power consumption of the oscillator and frequency divider, the two most power-consuming blocks in a PLL. Novel topologies for these two blocks are proposed which achieve ultra-low-power operation. Along with measured performance, mathematical analysis to derive rule-of-thumb design approaches are presented. Finally, the full transmitter is implemented using these blocks in a 130 nanometer CMOS process and is successfully tested for low-power operation

Energy-Efficient Wake-up Receivers for 915-MHz ISM Band Applications

Wake-up receiver (WuRx) is a well-known approach for optimizing the latency and power consumption of ultra-low power transceivers in wireless sensor nodes. Tuned RF (TRF) or Envelope Detection architecture is an appropriate topology for short-range Wireless Body Area Network (WBAN) applications, where achieving a very high sensitivity is not a priority. However, the demand for an improved sensitivity gets emphasized for longer transmission ranges. Regardless of the application, considering the existing trade-off between the power and sensitivity, design techniques and novel architectures are usually employed to optimize the power-sensitivity product. Moreover, considering the negative impact of higher data rate on the sensitivity, the energy-sensitivity product can be a more reasonable figure of merit when comparing WuRx designs. In this thesis, the RF-subsampling architecture has been combined with the TRF receiver architecture as a first approach for improving the power-sensitivity product. The overall power consumption is reduced as a result of employing the subsampling topology with a low-frequency local oscillator (LO). Post layout simulations show that the proposed WuRx draws only 56 μA from a 0.5 V supply and exhibits an input sensitivity of -70 dBm for a data rate of 100 kbps. The chip occupies an area of 0.15 mm2 and is fabricated with TSMC 90nm CMOS technology. Another major contribution of this work is to propose and implement a novel dual-mode ultra-low-power WuRx based on the subsampling topology, which not only reduces the overall power consumption but also optimizes the energy-sensitivity product of the receiver. During the typical mode of operation known as the Monitoring (MO) mode, the start frame bits are received at a rate of as low as 10 kbps. Having received the true preamble bits in the MO mode, the remaining wake-up pattern bits are received at a higher rate of 200 kbps during the Identifier (ID) mode. By lowering the gain of the front-end amplifier in the MO mode, the power dissipation is reduced, which in turn causes an increase in the overall noise figure of the receiver. However, adequate sensitivity and hence an optimized energy-sensitivity product is maintained by intentionally lowering the data rate as well as the detection bandwidth of the receiver in the MO mode. The proposed wake-up receiver has been designed and fabricated in IBM 130 nm technology with a core size of about 0.2 mm2 for the target frequency range of 902-928 MHz. The measured results show that the proposed dual-mode receiver achieves a sensitivity of -78.5 dBm and -75 dBm while dissipating an average power of 16.4 µW and 22.9 µW during MO and ID modes, respectively