Deterministic Jitter in Broadband Communication

The past decade has witnessed a drastic change in the design of high-speed serial links. While Silicon fabrication technology has produced smaller, faster transistors, transmission line interconnects between chips and through backplanes have not substantially improved and have a practical bandwidth of around 3GHz. As serial link speeds increase, new techniques must be introduced to overcome the bandwidth limitation and maintain digital signal integrity. This thesis studies timing issues pertaining to bandwidth-limited interconnects. Jitter is defined as the timing uncertainty at a threshold used to detect the digital signal. Reliable digital communication requires minimizing jitter. The analysis and modeling presented here focuses on two types of deterministic jitter. First, dispersion of the digital signal in a bandwidth-limited channel creates data-dependent jitter. Our analysis links data sequences to unique timing deviations through the channel response and is shown for general linear time-invariant systems. A Markov model is constructed to study the impact of jitter on the operation of the serial link and provide insight in circuit performance. Second, an analysis of bounded-uncorrected jitter resulting from crosstalk induced in parallel serial links is presented. Timing equalization is introduced to improve the signal integrity of high-speed links. The analysis of deterministic jitter leads to novel techniques for compensating the timing ambiguity in the received data. Data-dependent jitter equalization is discussed at both the receiver, where it complements the operation of clock and data recovery circuits, and as a phase pre-emphasis technique. Crosstalk-induced, bounded-uncorrected jitter can also be compensated. By detecting electromagnetic modes between neighboring serial links, a transmitter or receiver anticipates the timing deviation that has occurred along the transmission line. Finally, we discuss a new circuit technique for submillimeter integrated circuits. Demands of wireless communication and the high speed of Silicon Germanium transistors provide opportunities for unique radio architectures for submillimeter integrated circuits. Scalable, fully-integrated phased arrays control a radiated beam pattern electronically through tiling multiple chips. Coupled-oscillator arrays are used for the first time to subharmonically injection-lock across a chip or between multiple chips to provide phase coherence across an array.</p

차세대 HBM 용 고집적, 저전력 송수신기 설계

학위논문 (박사) -- 서울대학교 대학원 : 공과대학 전기·정보공학부, 2020. 8. 정덕균.This thesis presents design techniques for high-density power-efficient transceiver for the next-generation high bandwidth memory (HBM). Unlike the other memory interfaces, HBM uses a 3D-stacked package using through-silicon via (TSV) and a silicon interposer. The transceiver for HBM should be able to solve the problems caused by the 3D-stacked package and TSV. At first, a data (DQ) receiver for HBM with a self-tracking loop that tracks a phase skew between DQ and data strobe (DQS) due to a voltage or thermal drift is proposed. The self-tracking loop achieves low power and small area by uti-lizing an analog-assisted baud-rate phase detector. The proposed pulse-to-charge (PC) phase detector (PD) converts the phase skew to a voltage differ-ence and detects the phase skew from the voltage difference. An offset calibra-tion scheme that can compensates for a mismatch of the PD is also proposed. The proposed calibration scheme operates without any additional sensing cir-cuits by taking advantage of the write training of HBM. Fabricated in 65 nm CMOS, the DQ receiver shows a power efficiency of 370 fJ/b at 4.8 Gb/s and occupies 0.0056 mm2. The experimental results show that the DQ receiver op-erates without any performance degradation under a ± 10% supply variation. In a second prototype IC, a high-density transceiver for HBM with a feed-forward-equalizer (FFE)-combined crosstalk (XT) cancellation scheme is pre-sented. To compensate for the XT, the transmitter pre-distorts the amplitude of the FFE output according to the XT. Since the proposed XT cancellation (XTC) scheme reuses the FFE implemented to equalize the channel loss, additional circuits for the XTC is minimized. Thanks to the XTC scheme, a channel pitch can be significantly reduced, allowing for the high channel density. Moreover, the 3D-staggered channel structure removes the ground layer between the verti-cally adjacent channels, which further reduces a cross-sectional area of the channel per lane. The test chip including 6 data lanes is fabricated in 65 nm CMOS technology. The 6-mm channels are implemented on chip to emulate the silicon interposer between the HBM and the processor. The operation of the XTC scheme is verified by simultaneously transmitting 4-Gb/s data to the 6 consecutive channels with 0.5-um pitch and the XTC scheme reduces the XT-induced jitter up to 78 %. The measurement result shows that the transceiver achieves the throughput of 8 Gb/s/um. The transceiver occupies 0.05 mm2 for 6 lanes and consumes 36.6 mW at 6 x 4 Gb/s.본 논문에서는 차세대 HBM을 위한 고집적 저전력 송수신기 설계 방법을 제안한다. 첫 번째로, 전압 및 온도 변화에 의한 데이터와 클럭 간 위상 차이를 보상할 수 있는 자체 추적 루프를 가진 데이터 수신기를 제안한다. 제안하는 자체 추적 루프는 데이터 전송 속도와 같은 속도로 동작하는 위상 검출기를 사용하여 전력 소모와 면적을 줄였다. 또한 메모리의 쓰기 훈련 (write training) 과정을 이용하여 효과적으로 위상 검출기의 오프셋을 보상할 수 있는 방법을 제안한다. 제안하는 데이터 수신기는 65 nm 공정으로 제작되어 4.8 Gb/s에서 370 fJ/b을 소모하였다. 또한 10 % 의 전압 변화에 대하여 안정적으로 동작하는 것을 확인하였다. 두 번째로, 피드 포워드 이퀄라이저와 결합된 크로스 토크 보상 방식을 활용한 고집적 송수신기를 제안한다. 제안하는 송신기는 크로스 토크 크기에 해당하는 만큼 송신기 출력을 왜곡하여 크로스 토크를 보상한다. 제안하는 크로스 토크 보상 방식은 채널 손실을 보상하기 위해 구현된 피드 포워드 이퀄라이저를 재활용함으로써 추가적인 회로를 최소화한다. 제안하는 송수신기는 크로스 토크가 보상 가능하기 때문에, 채널 간격을 크게 줄여 고집적 통신을 구현하였다. 또한 집적도를 더 증가시키기 위해 세로로 인접한 채널 사이의 차폐 층을 제거한 적층 채널 구조를 제안한다. 6개의 송수신기를 포함한 프로토타입 칩은 65 nm 공정으로 제작되었다. HBM과 프로세서 사이의 silicon interposer channel 을 모사하기 위한 6 mm 의 채널이 칩 위에 구현되었다. 제안하는 크로스 토크 보상 방식은 0.5 um 간격의 6개의 인접한 채널에 동시에 데이터를 전송하여 검증되었으며, 크로스 토크로 인한 지터를 최대 78 % 감소시켰다. 제안하는 송수신기는 8 Gb/s/um 의 처리량을 가지며 6 개의 송수신기가 총 36.6 mW의 전력을 소모하였다.CHAPTER 1 INTRODUCTION 1 1.1 MOTIVATION 1 1.2 THESIS ORGANIZATION 4 CHAPTER 2 BACKGROUND ON HIGH-BANDWIDTH MEMORY 6 2.1 OVERVIEW 6 2.2 TRANSCEIVER ARCHITECTURE 10 2.3 READ/WRITE OPERATION 15 2.3.1 READ OPERATION 15 2.3.2 WRITE OPERATION 19 CHAPTER 3 BACKGROUNDS ON COUPLED WIRES 21 3.1 GENERALIZED MODEL 21 3.2 EFFECT OF CROSSTALK 26 CHAPTER 4 DQ RECEIVER WITH BAUD-RATE SELF-TRACKING LOOP 29 4.1 OVERVIEW 29 4.2 FEATURES OF DQ RECEIVER FOR HBM 33 4.3 PROPOSED PULSE-TO-CHARGE PHASE DETECTOR 35 4.3.1 OPERATION OF PULSE-TO-CHARGE PHASE DETECTOR 35 4.3.2 OFFSET CALIBRATION 37 4.3.3 OPERATION SEQUENCE 39 4.4 CIRCUIT IMPLEMENTATION 42 4.5 MEASUREMENT RESULT 46 CHAPTER 5 HIGH-DENSITY TRANSCEIVER FOR HBM WITH 3D-STAGGERED CHANNEL AND CROSSTALK CANCELLATION SCHEME 57 5.1 OVERVIEW 57 5.2 PROPOSED 3D-STAGGERED CHANNEL 61 5.2.1 IMPLEMENTATION OF 3D-STAGGERED CHANNEL 61 5.2.2 CHANNEL CHARACTERISTICS AND MODELING 66 5.3 PROPOSED FEED-FORWARD-EQUALIZER-COMBINED CROSSTALK CANCELLATION SCHEME 72 5.4 CIRCUIT IMPLEMENTATION 77 5.4.1 OVERALL ARCHITECTURE 77 5.4.2 TRANSMITTER WITH FFE-COMBINED XTC 79 5.4.3 RECEIVER 81 5.5 MEASUREMENT RESULT 82 CHAPTER 6 CONCLUSION 93 BIBLIOGRAPHY 95 초 록 102Docto

Hybrid NRZ/Multi-Tone Signaling for High-Speed Low-Power Wireline Transceivers

Over the past few decades, incessant growth of Internet networking traffic and High-Performance Computing (HPC) has led to a tremendous demand for data bandwidth. Digital communication technologies combined with advanced integrated circuit scaling trends have enabled the semiconductor and microelectronic industry to dramatically scale the bandwidth of high-loss interfaces such as Ethernet, backplane, and Digital Subscriber Line (DSL). The key to achieving higher bandwidth is to employ equalization technique to compensate the channel impairments such as Inter-Symbol Interference (ISI), crosstalk, and environmental noise. Therefore, todayâs advanced input/outputs (I/Os) has been equipped with sophisticated equalization techniques to push beyond the uncompensated bandwidth of the system. To this end, process scaling has continually increased the data processing capability and improved the I/O performance over the last 15 years. However, since the channel bandwidth has not scaled with the same pace, the required signal processing and equalization circuitry becomes more and more complicated. Thereby, the energy efficiency improvements are largely offset by the energy needed to compensate channel impairments. In this design paradigm, re-thinking about the design strategies in order to not only satisfy the bandwidth performance, but also to improve power-performance becomes an important necessity. It is well known in communication theory that coding and signaling schemes have the potential to provide superior performance over band-limited channels. However, the choice of the optimum data communication algorithm should be considered by accounting for the circuit level power-performance trade-offs. In this thesis we have investigated the application of new algorithm and signaling schemes in wireline communications, especially for communication between microprocessors, memories, and peripherals. A new hybrid NRZ/Multi-Tone (NRZ/MT) signaling method has been developed during the course of this research. The system-level and circuit-level analysis, design, and implementation of the proposed signaling method has been performed in the frame of this work, and the silicon measurement results have proved the efficiency and the robustness of the proposed signaling methodology for wireline interfaces. In the first part of this work, a 7.5 Gb/s hybrid NRZ/MT transceiver (TRX) for multi-drop bus (MDB) memory interfaces is designed and fabricated in 40 nm CMOS technology. Reducing the complexity of the equalization circuitry on the receiver (RX) side, the proposed architecture achieves 1 pJ/bit link efficiency for a MDB channel bearing 45 dB loss at 2.5 GHz. The measurement results of the first prototype confirm that NRZ/MT serial data TRX can offer an energy-efficient solution for MDB memory interfaces. Motivated by the satisfying results of the first prototype, in the second phase of this research we have exploited the properties of multi-tone signaling, especially orthogonality among different sub-bands, to reduce the effect of crosstalk in high-dense wireline interconnects. A four-channel transceiver has been implemented in a standard CMOS 40 nm technology in order to demonstrate the performance of NRZ/MT signaling in presence of high channel loss and strong crosstalk noise. The proposed system achieves 1 pJ/bit power efficiency, while communicating over a MDB memory channel at 36 Gb/s aggregate data rate

Design Techniques for High Performance Serial Link Transceivers

Increasing data rates over electrical channels with significant frequency-dependent loss is difficult due to excessive inter-symbol interference (ISI). In order to achieve sufficient link margins at high rates, I/O system designers implement equalization in the transmitters and are motivated to consider more spectrally-efficient modulation formats relative to the common PAM-2 scheme, such as PAM-4 and duobinary. The first work, reviews when to consider PAM-4 and duobinary formats, as the modulation scheme which yields the highest system margins at a given data rate is a function of the channel loss profile, and presents a 20Gb/s triple-mode transmitter capable of efficiently implementing these three modulation schemes and three-tap feedforward equalization. A statistical link modeling tool, which models ISI, crosstalk, random noise, and timing jitter, is developed to compare the three common modulation formats operating on electrical backplane channel models. In order to improve duobinary modulation efficiency, a low-power quarter-rate duobinary precoder circuit is proposed which provides significant timing margin improvement relative to full-rate precoders. Also as serial I/O data rates scale above 10 Gb/s, crosstalk between neighboring channels degrades system bit-error rate (BER) performance. The next work presents receive-side circuitry which merges the cancellation of both near-end and far-end crosstalk (NEXT/FEXT) and can automatically adapt to different channel environments and variations in process, voltage, and temperature. NEXT cancellation is realized with a novel 3-tap FIR filter which combines two traditional FIR filter taps and a continuous-time band-pass filter IIR tap for efficient crosstalk cancellation, with all filter tap coefficients automatically determined via an ondie sign-sign least-mean-square (SS-LMS) adaptation engine. FEXT cancellation is realized by coupling the aggressor signal through a differentiator circuit whose gain is automatically adjusted with a power-detection-based adaptation loop. In conclusion, the proposed architectures in the transmitter side and receiver side together are to be good solution in the high speed I/O serial links to improve the performance by overcome the physical channel loss and adjacent channel noise as the system becomes complicated

An Eight lanes 7Gb/s/pin Source Synchronous Single-Ended RX with Equalization and Far-End Crosstalk Cancellation for Backplane Channels

This paper presents a versatile crosstalk cancellation scheme for single-ended multi-lane backplane links. System-level investigations show that a scheme, which combines analog filters and decision-feedback crosstalk compensation on the receiver (RX) side only, can efficiently remove crosstalk patterns in straight channels as well as boards with reflections due to via stubs. An eight-lane single-ended RX has been manufactured in 32-nm SOI CMOS to validate our findings. A CTLE and eight-tap decision feedback equalizer equalize the channel without transmitter feedforward equalizer. A continuous time crosstalk canceller reduces precursors by nearest neighbors, while the residual postcursors from all aggressors are suppressed by direct feedback 7x8-tap decision-feedback crosstalk canceller (DFXC). Measurements with flip-chip packaged RX show that the RX macro can equalize both a 30-dB insertion loss single-ended channel with 0-dB signal-to-crosstalk at Nyquist and a channel with 28-dB attenuation with the signal-to-crosstalk ratio of 6 dB combined with reflections due to via stubs. The RX operates up to 7 Gb/s/pin with PRBS11 data at bit error rate (BER) <10⁻¹², and occupies 300x350 μm² with an energy efficiency of 5.9 mW/Gb/s from 1-V supply

대역폭 증대 기술을 이용한 전력 효율적 고속 송신 시스템 설계

학위논문(박사) -- 서울대학교대학원 : 공과대학 전기·정보공학부, 2022.2. 정덕균.The high-speed interconnect at the datacenter is being more crucial as 400 Gb Ethernet standards are developed. At the high data rate, channel loss re-quires bandwidth extension techniques for transmitters, even for short-reach channels. On the other hand, as the importance of east-to-west connection is rising, the data center architectures are switching to spine-leaf from traditional ones. In this trend, the number of short-reach optical interconnect is expected to be dominant. The vertical-cavity surface-emitting laser (VCSEL) is a com-monly used optical modulator for short-reach interconnect. However, since VCSEL has low bandwidth and nonlinearity, the optical transmitter also needs bandwidth-increasing techniques. Additionally, the power consumption of data centers reaches a point of concern to affect climate change. Therefore, this the-sis focuses on high-speed, power-efficient transmitters for data center applica-tions. Before the presenting circuit design, bandwidth extension techniques such as fractionally-spaced feed-forward equalizer (FFE), on-chip transmission line, inductive peaking, and T-coil are mathematically analyzed for their effec-tiveness. For the first chip, a power and area-efficient pulse-amplitude modulation 4 (PAM-4) transmitter using 3-tap FFE based on a slow-wave transmission line is presented. A passive delay line is adopted for generating an equalizer tap to overcome the high clocking power consumption. The transmission line achieves a high slow-wave factor of 15 with double floating metal shields around the differential coplanar waveguide. The transmitter includes 4:1 multi-plexers (MUXs) and a quadrature clock generator for high-speed data genera-tion in a quarter-rate system. The 4:1 MUX utilizes a 2-UI pulse generator, and the input configuration is determined by qualitative analysis. The chip is fabri-cated in 65 nm CMOS technology and occupies an area of 0.151 mm2. The proposed transmitter system exhibits an energy efficiency of 3.03 pJ/b at the data rate of 48 Gb/s with PAM-4 signaling. The second chip presents a power-efficient PAM-4 VCSEL transmitter using 3-tap FFE and negative-k T-coil. The phase interpolators (PIs) generate frac-tionally-spaced FFE tap and correct quadrature phase error. The PAM-4 com-bining 8:1 MUX is proposed rather than combining at output driver with double 4:1 MUXs to reduce serializing power consumption. T-coils at the internal and output node increase the bandwidth and remove inter-symbol interference (ISI). The negative-k T-coil at the output network increases the bandwidth 1.61 times than without T-coil. The VCSEL driver is placed on the high VSS domain for anode driving and power reduction. The chip is fabricated in 40 nm CMOS technology. The proposed VCSEL transmitter operates up to 48 Gb/s NRZ and 64 Gb/s PAM-4 with the power efficiency of 3.03 pJ/b and 2.09 pJ/b, respec-tively.400Gb 이더넷 표준이 개발됨에 따라 데이터 센터의 고속 상호 연결이 더욱 중요해지고 있다. 높은 데이터 속도에서의 채널 손실에 의해 단거리 채널의 경우에도 송신기에 대한 대역폭 확장 기술이 필요하다. 한편, 데이터 센터 내 동-서 연결의 중요성이 높아지면서 데이터 센터 아키텍처가 기존의 아키텍처에서 스파인-리프로 전환되고 있다. 이러한 추세에서 단거리 광학 인터커넥트의 수가 점차 우세해질 것으로 예상된다. 수직 캐비티 표면 방출 레이저(VCSEL)는 일반적으로 단거리 상호 연결을 위해 사용되는 광학 모듈레이터이다. VCSEL은 낮은 대역폭과 비선형성을 가지고 있기 때문에, 광 송신기도 대역폭 증가 기술을 필요로 한다. 또한, 데이터 센터의 전력 소비는 기후 변화에 영향을 미칠 수 있는 우려 지점에 도달했다. 따라서, 본 논문은 데이터 센터 응용을 위한 고속 전력 효율적인 송신기에 초점을 맞추고 있다. 회로 설계를 제시하기 전에, 부분 간격 피드-포워드 이퀄라이저 (FFE), 온칩 전송선로, 인덕터, T-코일과 같은 대역폭 확장 기술을 수학적으로 분석한다. 첫 번째 칩은 저속파 전송선로를 기반으로 한 3-탭 FFE를 사용하는 전력 및 면적 효율적인 펄스-진폭-변조 4(PAM-4) 송신기를 제시한다. 높은 클럭 전력 소비를 극복하기 위해 이퀄라이저 탭 생성을 위해 수동소자 지연 라인을 채택했다. 전송 라인은 차동 동일평면도파관 주위에 이중 플로팅 금속 차폐를 사용하여 15의 높은 전달속도 감쇠를 달성한다. 송신기에는 4:1 멀티플렉서(MUX)와 4-위상 클럭 생성기가 포함되어 있다. 4:1 MUX는 2-UI 펄스 발생기를 사용하며, 정성 분석에 의해 입력 구성이 결정된다. 이 칩은 65 nm CMOS 기술로 제작되었으며 0.151 mm2의 면적을 차지한다. 제안된 송신기 시스템은 PAM-4 신호와 함께 48 Gb/s의 데이터 속도에서 3.03 pJ/b의 에너지 효율을 보여준다. 두 번째 칩에서는 3-탭 FFE 및 역회전 T-코일을 사용하는 전력 효율적인 PAM-4 VCSEL 송신기를 제시한다. 위상 보간기(PI)는 부분 간격 FFE 탭을 생성하고 4-위상 클럭 오류를 수정하는 데 사용된다. 직렬화 전력 소비를 줄이기 위해 출력 드라이버에서 MSB와 LSB를 두 개의 4:1 MUX를 통해 결합하는 대신 8:1 MUX를 통해 PAM-4로 결합하는 회로가 제안된다. 내부 및 출력 노드에서 T-코일은 대역폭을 증가시키고 기호 간 간섭(ISI)을 제거한다. 출력 네트워크에서 역회전 T-코일은 T-코일이 없는 경우보다 대역폭을 1.61배 증가시킨다. VCSEL 드라이버는 양극 구동 및 전력 감소를 위해 높은 VSS 도메인에 배치된다. 이 칩은 40 nm CMOS 기술로 제작되었다. 제안된 VCSEL 송신기는 각각 3.03pJ/b와 2.09pJ/b의 전력 효율로 최대 48Gb/s NRZ와 64Gb/s PAM-4까지 작동한다.ABSTRACT I CONTENTS III LIST OF FIGURES V LIST OF TABLES IX CHAPTER 1 INTRODUCTION 1 1.1 MOTIVATION 1 1.2 THESIS ORGANIZATION 5 CHAPTER 2 BACKGROUND OF HIGH-SPEED INTERFACE 6 2.1 OVERVIEW 6 2.2 BASIS OF DATA CENTER ARCHITECTURE 9 2.3 SHORT-REACH INTERFACE STANDARDS 12 2.4 ANALYSES OF BANDWIDTH EXTENSION TECHNIQUES 16 2.4.1 FRACTIONALLY-SPACED FFE 16 2.4.2 TRANSMISSION LINE 21 2.4.3 INDUCTOR 24 2.4.4 T-COIL 33 CHAPTER 3 DESIGN OF 48 GB/S PAM-4 ELECTRICAL TRANSMITTER IN 65 NM CMOS 43 3.1 OVERVIEW 43 3.2 FFE BASED ON DOUBLE-SHIELDED COPLANAR WAVEGUIDE 46 3.2.1 BASIC CONCEPT 46 3.2.2 PROPOSED DOUBLE-SHIELDED COPLANAR WAVEGUIDE 47 3.3 DESIGN CONSIDERATION ON 4:1 MUX 50 3.4 PROPOSED PAM-4 ELECTRICAL TRANSMITTER 53 3.5 MEASUREMENT 57 CHAPTER 4 DESIGN OF 64 GB/S PAM-4 OPTICAL TRANSMITTER IN 40 NM CMOS 64 4.1 OVERVIEW 64 4.2 DESIGN CONSIDERATION OF OPTICAL TRANSMITTER 66 4.3 PROPOSED PAM-4 VCSEL TRANSMITTER 69 4.4 MEASUREMENT 82 CHAPTER 5 CONCLUSIONS 88 BIBLIOGRAPHY 90 초 록 101박

An Energy-Efficient Reconfigurable Mobile Memory Interface for Computing Systems

The critical need for higher power efficiency and bandwidth transceiver design has significantly increased as mobile devices, such as smart phones, laptops, tablets, and ultra-portable personal digital assistants continue to be constructed using heterogeneous intellectual properties such as central processing units (CPUs), graphics processing units (GPUs), digital signal processors, dynamic random-access memories (DRAMs), sensors, and graphics/image processing units and to have enhanced graphic computing and video processing capabilities. However, the current mobile interface technologies which support CPU to memory communication (e.g. baseband-only signaling) have critical limitations, particularly super-linear energy consumption, limited bandwidth, and non-reconfigurable data access. As a consequence, there is a critical need to improve both energy efficiency and bandwidth for future mobile devices.;The primary goal of this study is to design an energy-efficient reconfigurable mobile memory interface for mobile computing systems in order to dramatically enhance the circuit and system bandwidth and power efficiency. The proposed energy efficient mobile memory interface which utilizes an advanced base-band (BB) signaling and a RF-band signaling is capable of simultaneous bi-directional communication and reconfigurable data access. It also increases power efficiency and bandwidth between mobile CPUs and memory subsystems on a single-ended shared transmission line. Moreover, due to multiple data communication on a single-ended shared transmission line, the number of transmission lines between mobile CPU and memories is considerably reduced, resulting in significant technological innovations, (e.g. more compact devices and low cost packaging to mobile communication interface) and establishing the principles and feasibility of technologies for future mobile system applications. The operation and performance of the proposed transceiver are analyzed and its circuit implementation is discussed in details. A chip prototype of the transceiver was implemented in a 65nm CMOS process technology. In the measurement, the transceiver exhibits higher aggregate data throughput and better energy efficiency compared to prior works

Investigation of the limiting fibre nonlinearities and their suppression in 40Gbit/s optical transmission systems.

This thesis investigates the fundamental limitations to optical transmission at a bit-rate of 40Gbit/s. The signal distortion due to nonlinear effects, noise and dispersion are analysed and techniques for their suppression through dispersion management and optimum choice of modulation format are demonstrated. The high launch powers required for overcoming noise from the amplifiers result in an increase in fibre nonlinearities. Transmission at 40Gbit/s favours the RZ modulation format. However, RZ signals were found to be limited by intra-channel cross phase modulation (IXPM) and intra-channel four-wave-mixing (IFWM). These intra-channel nonlinear effects take place as a result of nonlinear interaction between overlapping pulses of the same wavelength channel. Minimising such pulse overlap by controlling the dispersion-induced pulse broadening during propagation in the fibre was investigated by reducing the fibre local dispersion and by pre-compensating the signal at the transmitter. Dispersion compensation using higher-order-mode devices with high nonlinear tolerance was also investigated, enabling transmission over in-line pre-compensated amplifier spans. In the second part of this thesis, the nonlinear tolerance of the RZ modulation format was increased by use of alternate-polarisation and alternate-phase between adjacent pulses. These techniques were found to improve the transmission performance by approximately 50% and required simple modifications to the transmitter only. These advanced RZ signals were found to be compatible with dispersion management techniques. However, the optimum pre-compensation at the transmitter was found to be dependent on the modulation format and dominant intra-channel effect. A novel modulation format combining alternate-polarisation and phase simultaneously was demonstrated for maximum nonlinear suppression without the use of dispersion management. Finally, a new experimental technique was demonstrated for the investigation of dispersion tolerance. It was found that the choice of optimum modulation format requires a trade-off between nonlinear tolerance and dispersion tolerance. The results of this work can be applied to optimise the design rules of future optical networks

Modeling and estimation of crosstalk across a channel with multiple, non-parallel coupling and crossings of multiple aggressors in practical PCBS

In Section 1, the focus is on alleviating the modeling challenges by breaking the overall geometry into small, unique sections and using either a Full-Wave or fast equivalent per-unit-length (Eq. PUL) resistance, inductance, conductance, capacitance (RLGC) method or a partial element equivalent circuit (PEEC) for the broadside coupled traces that cross at an angle. The simulation challenge is resolved by seamlessly integrating the models into a statistical simulation tool that is able to quantify the eye opening at BERs that would help electrical designers in locating crosstalk sensitive regions in the high speed backplane channel designs. Section 2 investigates the FEXT crosstalk impact on eye opening at a specified bit error rate (BER) at different signal speeds for broadside and edge side differential coupled traces in inhomogeneous media and compared the results against homogeneous media models. A set of design guidelines regarding the material, coupled length and stackup parameter selection is formulated for designers based on the signaling speeds. The major objective of the study in Section 3 is to determine quantitatively the effect of crosstalk due to periodic broadside coupled routing. Another objective is to help designers figure out the “dos” and “don’ts” of broadside coupled routing for higher signaling rates. A new methodology is proposed in Section 4 to generate BER contours that capture the Tx driver jitter and ISI through the channel accurately using unique waveforms created from truth table bit combinations. It utilizes 2N short N bit patterns as waveforms and jitter correlation from current bit pattern into adjacent bit patterns to get equivalent transient simulation of a very large bit pattern. --Abstract, page iii