6 research outputs found
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Integrated Circuits and Systems for Millimeter-Wave Frequencies
In the first section of this thesis, mm-wave circuit- and system-level solutions for addition of multi-user service to conventional multi-antenna phased array architectures will be introduced. The proposed architecture will enhance the link capacity, co-channel user service and hardware cost compared to conventional solutions. Theory and design of the circuits and system are detailed and comprehensive measurement results are presented verifying the system-level functionality. First section is named A Millimeter-Wave Partially-Overlapped Beamforming-MIMO Receiver: Theory, Design, and Implementation. More specifically, this section presents an analysis and design of a partially-overlapped beamforming-MIMO architecture capable of achieving higher beamforming and spatial multiplexing gains with lower number of elements compared to conventional architectures. As a proof of concept, a 4-element beamforming-MIMO receiver (RX) covering 64-67 GHz frequency band enabling 2-stream concurrent reception is designed and measured. By partitioning the RX elements into two clusters and partially overlapping these clusters to create two 3-element beamformers, both phased-array (coherent beamforming) as well as MIMO (spatial multiplexing) features are simultaneously acquired. 6-bit phase shifters with 360° phase control and 5-bit VGAs with 11 dB range are designed to enable steering of the two RX clusters toward two arbitrary angular locations corresponding to two users. Fabricated in a 130-nm SiGe BiCMOS process, the RX achieves a 30.15 dB maximum direct conversion gain and a 9.8 dB minimum noise figure (NF) across 548 MHz IF bandwidth. S-parameter-based array factor measurements verify spatial filtering of the interference and spatial multiplexing in this RX chip.In the second section of this thesis, energy-efficient ultra-high speed transceiver architectures will be presented. Current high-speed transceivers rely on high-sampling-rate high-resolution power-hungry analog-to-digital converters or digital-to-analog converters at the interface of analog and digital circuitries. However, design of these backend data-converters are extremely power-hungry at very high speeds in a fully-integrated end-to-end scenario (i.e. RF-to-Bits, Bits-to-RF). Novel system-level architectures will be presented that obviate the need for such costly data converters and will significantly relax the complexity of digital signal-processing. The proposed architecture will result in orders of magnitude energy saving at ultra-high speeds. Theory, design, and measurement results of the highest-speed, highly energy-efficient fully-integrated end-to-end transceiver will be discussed in this section. Second section is named A Millimeter-Wave Energy-Efficient Direct-Demodulation Receiver: Theory, Design, and Implementation. More precisely, this section presents the theory, design, and implementation of an 8PSK direct-demodulation receiver based on a novel multi-phase RF-correlation concept. The output of this RF-to-bits receiver architecture is demodulated bits, obviating the need for power-hungry high-speed-resolution data converters. A single-channel 115-135-GHz receiver prototype was fabricated in a 55-nm SiGe BiCMOS process. A max conversion gain of 32 dB and a min noise figure (NF) of 10.3 dB was measured. A data-rate of 36 Gbps was wirelessly measured at 30 cm distance with the received 8PSK signal being directly demodulated on-chip at a bit-error-rate (BER) of 1e-6. The measured receiver sensitivity at this BER is -41.28 dBm. The prototype occupies 2.5 by 3.5 mm squared of die area including PADs and test circuits (2.5 mm squared active area) and consumes a total DC power of 200.25 mW
High-Efficiency Millimeter-Wave Front-Ends for Large Phased-Array Transmitters
The ever-increasing demand for wireless broadband connectivity requires infrastructure capable of supporting data transfer rates at multi-Gbps. To accommodate such heavy traffic, the channel capacity for the given spectrum must be utilized as efficiently as possible. Wideband millimeter-wave phased-array systems can enhance the capacity of the channel by providing multiple steerable directional beams.
However the cost, complexity, and high power consumption of phased-array systems are key barriers to the commercialization of such technology. Silicon-based beam-former chips and scalable phased-array technology offer promising solutions to lower the cost of phased-array systems. However, the implementation of low-power phased-array architectures is still a challenge. Millimeter-wave power generation in silicon beam-formers suffers from low efficiency. The stringent linearity requirements for multi-beam wideband arrays further limits the achievable efficiency.
In scalable phased-arrays, each module consists of an antenna sub-array and a beam-former chip that feeds the antenna elements. To improve efficiency, a design methodology that considers the beam-former chip and the antenna array as one entity is necessary.
In this thesis, power-efficient solutions for a millimeter-wave phased-array transmitter are studied and different high-efficiency power amplifier structures for broadband applications are proposed.
Initially, the design of a novel 27-30 GHz RF front-end consisting of a variable gain amplifier, a 360 degree phase shifter, and a two-stage linear power amplifier with output power of 12 dBm is described. It is fabricated using 0.13 SiGe technology. This chip serves as the RF core of a beam-former chip with eight outputs for feeding a 22 dual-feed sub-array. Such sub-arrays are used as part of large phased-arrays for SATCOM infrastructure. Measurement results show 26.7 \% total efficiency for the designed chip. The chip achieves the highest efficiency among Ka-band phased-array transmitters reported in the literature.
In addition, original transformer-based output matching structures are proposed for harmonic-tuned power amplifiers. Harmonic-tuned power amplifiers have high peak-efficiency but their complicated output matching structure can limit their use in beam-former RF front-ends. The proposed output matching structures have the layout footprint of a transformer, making their use in beam-former chips feasible. A 26-38 GHz power amplifier based on a non-inverting 1:1 transformer is fabricated. A measured efficiency of more than 27 \% is achieved across the band with an output power of 12 dBm. Furthermore, two continuous class power amplifiers using 1:1 inverting transformers are described. Simulation results show a peak-efficiency of 35 \% and output power of 12 dBm from 24 to 30 GHz. A common-base power amplifier with inverting transformer output matching is also demonstrated. This amplifier achieves a peak-efficiency of 42 \% and peak output power of 16 dBm.
Finally, a low-loss Ka-band re-configurable output matching structure based on tunable lines is proposed and implemented. A double-stub matching structure with three tunable segments is proposed to maximize the impedance matching coverage. This structure can potentially compensate for the antenna impedance variation in phased-array antennas
KEY FRONT-END CIRCUITS IN MILLIMETER-WAVE SILICON-BASED WIRELESS TRANSMITTERS FOR PHASED-ARRAY APPLICATIONS
Millimeter-wave (mm-Wave) phased arrays have been widely used in numerous wireless systems to perform beam forming and spatial filtering that can enhance the equivalent isotropically radiated power (EIRP) for the transmitter (TX). Regarding the existing phased-array architectures, an mm-Wave transmitter includes several building blocks to perform the desired delivered power and phases for wireless communication.
Power amplifier (PA) is the most important building block. It needs to offer several advantages, e.g., high efficiency, broadband operation and high linearity. With the recent escalation of interest in 5G wireless communication technologies, mm-Wave transceivers at the 5G frequency bands (e.g., 28 GHz, 37 GHz, 39 GHz, and 60 GHz) have become an important topic in both academia and industry. Thus, PA design is a critical obstacle due to the challenges associated with implementing wideband, highly efficient and highly linear PAs at mm-Wave frequencies. In this dissertation, we present several PA design innovations to address the aforementioned challenges.
Additionally, phase shifter (PS) also plays a key role in a phased-array system, since it governs the beam forming quality and steering capabilities. A high-performance phase shifter should achieve a low insertion loss, a wide phase shifting range, dense phase shift angles, and good input/output matching.Ph.D
Radio Frequency and Millimeter Wave Circuit Component Design with SiGe BiCMOS Technology
The objective of this research is to study and leverage the unique properties and advantages of silicon-germanium (SiGe) heterojunction bipolar transistor (HBT) integrated circuit technologies to better design radio frequency (RF) and millimeter wave (mm-wave) circuit components. With recent developments, the high yield and modest cost silicon-based semiconductor technologies have proven to be attractive and cost-effective alternatives to high-performance III-V technology platforms. Between SiGe bipolar complementary metal-oxide-semiconductor (BiCMOS) technology and advanced RF complementary metal-oxide-semiconductor (CMOS) technology, the fundamental device-level differences between SiGe HBTs and field-effect transistors (FETs) grant SiGe HBTs clear advantages as well as unique design concerns. The work presented in this dissertation identifies several advantages and challenges on design using SiGe HBTs and provides design examples that exploit and address these unique benefits and problems with circuit component designs using SiGe HBTs.Ph.D
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Architectures and Integrated Circuits for Efficient, High-power "Digital'' Transmitters for Millimeter-wave Applications
This thesis presents architectures and integrated circuits for the implementation of energy-efficient, high-power "digital'' transmitters to realize high-speed long-haul links at millimeter-wave frequencies in nano-scale silicon-based processes