Continuous-time low-pass filters for integrated wideband radio receivers

This thesis concentrates on the design and implementation of analog baseband continuous-time low-pass filters for integrated wideband radio receivers. A total of five experimental analog baseband low-pass filter circuits were designed and implemented as a part of five single-chip radio receivers in this work. After the motivation for the research work presented in this thesis has been introduced, an overview of analog baseband filters in radio receivers is given first. In addition, a review of the three receiver architectures and the three wireless applications that are adopted in the experimental work of this thesis is presented. The relationship between the integrator non-idealities and integrator Q-factor, as well as the effect of the integrator Q-factor on the filter frequency response, are thoroughly studied on the basis of a literature review. The theoretical study that is provided is essential for the gm-C filter synthesis with non-ideal lossy integrators that is presented after the introduction of different techniques to realize integrator-based continuous-time low-pass filters. The filter design approach proposed for gm-C filters is original work and one of the main points in this thesis, in addition to the experimental IC implementations. Two evolution versions of fourth-order 10-MHz opamp-RC low-pass filters designed and implemented for two multicarrier WCDMA base-station receivers in a 0.25-µm SiGe BiCMOS technology are presented, along with the experimental results of both the low-pass filters and the corresponding radio receivers. The circuit techniques that were used in the three gm-C filter implementations of this work are described and a common-mode induced even-order distortion in a pseudo-differential filter is analyzed. Two evolution versions of fifth-order 240-MHz gm-C low-pass filters that were designed and implemented for two single-chip WiMedia UWB direct-conversion receivers in a standard 0.13-µm and 65-nm CMOS technology, respectively, are presented, along with the experimental results of both the low-pass filters and the second receiver version. The second UWB filter design was also embedded with an ADC into the baseband of a 60-GHz 65-nm CMOS radio receiver. In addition, a third-order 1-GHz gm-C low-pass filter was designed, rather as a test structure, for the same receiver. The experimental results of the receiver and the third gm-C filter implementation are presented

Design of a wideband variable gain amplifier

Synteettisapertuurinen tutka (SAR) on hyvin tunnettu tekniikka maanpinnan kuvantamiseen. Tässä diplomityössä on suunniteltu laajakaistainen säädettävä vahvistin, jota voidaan käyttää SAR:in suorasekoitusvastaanottimessa (DCR). Ensin näytetään kuinka tärkeät muuttujat, kuten esimerkiksi VGA:n vahvistus, kaistanleveys ja kohina, saadaan määritettyä vastaanottimen kokonaisvaatimuksista. Seuraavaksi esitetään yleisesti suunnittelutapa VGA:lle, jossa tunnistetaan VGA:n tärkeimmät suunnittelumoduulit. Laajakaistaiset asteet, joita voidaan käyttää VGA:n suunnittelussa, esitellään lyhyesti, kuten myös tekniikoita, joilla siirrosjännite saadaan kompensoitua. Seuraavaksi esitellään yksityiskohtaisesti kuinka VGA suunnitellaan. Työssä esitetään piensignaali- ja kohina-analyysit VGA:n vahvistusasteille kuten myös simulaatiotulokset. VGA on suunniteltu ja valmistettu 0.13 µm CMOS prosessilla. Piirikuvion jälkeiset simulaatiot on myös esitetty ja ne todentavat lopullisen piirikuvion toimivuutta. Lopuksi esitetään VGA:n mittaustulokset, jotka näyttävät, että halutut vahvistus ja kaistanleveys on saavutettu. Mikropiirin digitaalisen ohjauksen epätasaisesta toimivuudesta johtuen, VGA:n taajuusvasteessa näkyi vahvistuksen piikittämistä. VGA:n tulon kohinatiheyden mittaustulokset eri vahvistusasetuksilla on myös esitetty ja ne vastaavat hyvin simuloituja arvoja. Tulon 1 dB:n kompressiopiste ja tulon kolmannen kertaluvun keskinäismodulaatiosärön leikkauspiste on myös annettu VGA:lle. Yleisesti ottaen VGA:n toimintaa voidaan pitää onnistuneena SAR:ssa käytettävälle suorasekoitusvastaanottimelle.Synthetic Aperture Radar (SAR) is a well known technique for imaging the earth's surface. This thesis presents a wideband variable gain amplifier which can be used in the direct conversion receiver (DCR) for SAR. The thesis first introduces how to extract the important parameters i.e. gain, bandwidth and noise of the VGA from the overall receiver requirements. Next, a general design philosophy for the VGA is presented which identifies the main design modules in the amplifier. Also, a brief introduction to wideband stages and DC-offset compensation techniques is presented. Then a detailed explanation of the VGA design is given. Small-signal and noise analyses are presented for the VGA gain stages along with their simulation results. VGA post-layout simulation results are also shown to verify the functionality of the final layout drawn using 0.13 µm CMOS. At the end, measurement results for the VGA are given which show that the VGA achieved the desired gain and bandwidth. However, due to irregular operation of the digital control for the chip, the frequency response of the VGA showed gain peaking. The measured input noise density of the VGA at different gain settings is also given and it matched well with the simulated value. Moreover, the input 1 dB compression point and the third order input intercept point results for the VGA are also given. The overall operation of VGA was deemed satisfactory for the direct conversion receiver for SAR

Design of a Low Power 70MHz-110MHz Harmonic Rejection Filter with Class-AB Output Stage

An FM transmitter becomes the new feature in recent portable electronic development. A low power, integrable FM transmitter filter IC is required to meet the demand of FM transmitting feature. A low pass filter using harmonic rejection technique along with a low power class-AB output buffer is designed to meet the current market requirements on the FM transmitter chip. A harmonic rejection filter is designed to filter FM square wave signal from 70MHz to 110MHz into FM sine wave signal. Based on Fourier series, the harmonic rejection technique adds the phase shifted square waves to achieve better THD and less high frequency harmonics. The phase shifting is realized through a frequency divider, and the summation is implemented through a current summation circuit. A RC low pass filter with automatic tuning is designed to further attenuate unwanted harmonics. In this work, the filter's post layout simulation shows -53dB THD and harmonics above 800MHz attenuation of -99dB. The power consumption of the filter is less than 0.7mW. Output buffer stage is implemented through a resistor degenerated transconductor and a class-AB amplifier. Feedforward frequency compensation is applied to compensate the output class-AB stage, which extends the amplifier's operating bandwidth. A fully balanced class-AB driver is proposed to unleash the driving capability of common source output transistors. The output buffer reaches -43dB THD at 110MHz with 0.63Vpp output swing and drives 1mW into 50 load. The power consumption of the output buffer is 7.25mW. By using harmonic rejection technique, this work realizes the 70MHz-110MHz FM carrier filtering using TSMC 0.18um nominal process. Above 800MHz harmonics are attenuated to below -95dB. With 1.2V supply, the total power consumption including output buffer is 7.95mW. The total die area is 0.946mm2

Linearization and Efficiency Enhancement Techniques for RF and Baseband Analog Circuits

High linearity transmitters and receivers should be used to efficiently utilize the available channel bandwidth. Power consumption is also a critical factor that determines the battery life of portable devices and wireless sensors. Three base-band and RF building blocks are designed with the focus of high linearity and low power consumption. An architectural attenuation-predistortion linearization scheme for a wide range of operational transconductance amplifiers (OTAs) is proposed and demonstrated with a transconductance-capacitor (Gm-C) filter. The linearization technique utilizes two matched OTAs to cancel output harmonics, creating a robust architecture. Compensation for process variations and frequency-dependent distortion based on Volterra series analysis is achieved by employing a delay equalization scheme with on-chip programmable resistors. The distortion-cancellation technique enables an IM3 improvement of up to 22dB compared to a commensurate OTA without linearization. A proof-of-concept lowpass filter with the linearized OTAs has a measured IM3 < -70dB and 54.5dB dynamic range over its 195MHz bandwidth. Design methodology for high efficiency class D power amplifier is presented. The high efficiency is achieved by using higher current harmonic to achieve zero voltage switching (ZVS) in class D power amplifier. The matching network is used as a part of the output filter to remove the high order harmonics. Optimum values for passive circuit elements and transistor sizes have been derived in order to achieve the highest possible efficiency. The proposed power amplifier achieves efficiency close to 60 percent at 400 MHz for -2dBm of output power. High efficiency class A power amplifier using dynamic biasing technique is presented. The power consumption of the power amplifier changes dynamically according to the output signal level. Effect of dynamic bias on class A power amplifier linearity is analyzed and the results were verified using simulations. The linearity of the dynamically biased amplifier is improved by adjusting the preamplifier gain to guarantee constant overall gain for different input signal levels

SMARAD - Centre of Excellence in Smart Radios and Wireless Research - Activity Report 2008 - 2010

Centre of Excellence in Smart Radios and Wireless Research (SMARAD), originally established with the name Smart and Novel Radios Research Unit, is aiming at world-class research and education in Future radio and antenna systems, Cognitive radio, Millimetre wave and THz techniques, Sensors, and Materials and energy, using its expertise in RF, microwave and millimetre wave engineering, in integrated circuit design for multi-standard radios as well as in wireless communications. SMARAD has the Centre of Excellence in Research status from the Academy of Finland since 2002 (2002-2007 and 2008-2013). Currently SMARAD consists of five research groups from three departments, namely the Department of Radio Science and Engineering, Department of Micro and Nanosciences, and Department of Signal Processing and Acoustics, all within the Aalto University School of Electrical Engineering. The total number of employees within the research unit is about 100 including 8 professors, about 30 senior scientists and about 40 graduate students and several undergraduate students working on their Master thesis. The relevance of SMARAD to the Finnish society is very high considering the high national income from exports of telecommunications and electronics products. The unit conducts basic research but at the same time maintains close co-operation with industry. Novel ideas are applied in design of new communication circuits and platforms, transmission techniques and antenna structures. SMARAD has a well-established network of co-operating partners in industry, research institutes and academia worldwide. It coordinates a few EU projects. The funding sources of SMARAD are diverse including the Academy of Finland, EU, ESA, Tekes, and Finnish and foreign telecommunications and semiconductor industry. As a byproduct of this research SMARAD provides highest-level education and supervision to graduate students in the areas of radio engineering, circuit design and communications through Aalto University and Finnish graduate schools such as Graduate School in Electronics, Telecommunications and Automation (GETA). During years 2008 – 2010, 21 doctor degrees were awarded to the students of SMARAD. In the same period, the SMARAD researchers published 141 refereed journal articles and 333 conference papers

Development of Robust Analog and Mixed-Signal Circuits in the Presence of Process- Voltage-Temperature Variations

Continued improvements of transceiver systems-on-a-chip play a key role in the advancement of mobile telecommunication products as well as wireless systems in biomedical and remote sensing applications. This dissertation addresses the problems of escalating CMOS process variability and system complexity that diminish the reliability and testability of integrated systems, especially relating to the analog and mixed-signal blocks. The proposed design techniques and circuit-level attributes are aligned with current built-in testing and self-calibration trends for integrated transceivers. In this work, the main focus is on enhancing the performances of analog and mixed-signal blocks with digitally adjustable elements as well as with automatic analog tuning circuits, which are experimentally applied to conventional blocks in the receiver path in order to demonstrate the concepts. The use of digitally controllable elements to compensate for variations is exemplified with two circuits. First, a distortion cancellation method for baseband operational transconductance amplifiers is proposed that enables a third-order intermodulation (IM3) improvement of up to 22dB. Fabricated in a 0.13µm CMOS process with 1.2V supply, a transconductance-capacitor lowpass filter with the linearized amplifiers has a measured IM3 below -70dB (with 0.2V peak-to-peak input signal) and 54.5dB dynamic range over its 195MHz bandwidth. The second circuit is a 3-bit two-step quantizer with adjustable reference levels, which was designed and fabricated in 0.18µm CMOS technology as part of a continuous-time SigmaDelta analog-to-digital converter system. With 5mV resolution at a 400MHz sampling frequency, the quantizer's static power dissipation is 24mW and its die area is 0.4mm^2. An alternative to electrical power detectors is introduced by outlining a strategy for built-in testing of analog circuits with on-chip temperature sensors. Comparisons of an amplifier's measurement results at 1GHz with the measured DC voltage output of an on-chip temperature sensor show that the amplifier's power dissipation can be monitored and its 1-dB compression point can be estimated with less than 1dB error. The sensor has a tunable sensitivity up to 200mV/mW, a power detection range measured up to 16mW, and it occupies a die area of 0.012mm^2 in standard 0.18µm CMOS technology. Finally, an analog calibration technique is discussed to lessen the mismatch between transistors in the differential high-frequency signal path of analog CMOS circuits. The proposed methodology involves auxiliary transistors that sense the existing mismatch as part of a feedback loop for error minimization. It was assessed by performing statistical Monte Carlo simulations of a differential amplifier and a double-balanced mixer designed in CMOS technologies