Using Object-Oriented Database Technology to Develop a Multiple Domain Capability for Domain-Oriented Application Composition Systems

This thesis describes the design and implementation of a multiple domain capability for a domain-oriented application composition system, named Architect. The research goal was to show how object-oriented database management system (OODBMS) technology can be used to provide simultaneous access to multiple domain-oriented knowledge bases. Since the Architect system was originally designed using the object-oriented paradigm, insertion of OODBMS technology was relatively simple and many of the object-oriented concepts, such as inheritance and aggregation, proved beneficial. Inheritance was used to encapsulate domain knowledge by defining each domain as a subclass of Architect\u27s software architecture. Aggregation was used to allow applications to cross domain boundaries by nesting components from multiple domains in an application. To validate this approach, domain extensions to two existing domain models were implemented to make the domains compatible in a multiple domain environment, and applications containing objects from both the logic circuits and digital signal processing domains were successfully developed. One of the primary benefits of this research is the potential for greater reuse of objects. To satisfy new requirements, domain engineers can now search for and access objects from other domains as an alternative to implementing them in their own domains

Discrete time control of a push-pull power converter

The objective is the design of a discrete time controller in a push-pull power converter. The work figures out the issues related to the migration of the analog control to the digital one in power converters and both simulation and experimental results are performed to obtain a comparative evaluation of both proposals.This work apply digital control techniques in a DC/DC push-pull power converter. Sections include converter modelization, control design, simulations, implementation and experimental results

Signal acquisition challenges in mobile systems

In recent decades, the advent of mobile computing has changed human lives by providing information that was not available in the past. The mobile computing platform opens a new door to the connected world in which various forms of hand-held and wearable systems are ubiquitous. A single mobile device plays multiple roles and shapes human lives towards a better future. In these systems, sensor-based data acquisition plays an essential role in generating and providing useful information. The increased number of sensors is embedded in a single device in order to process various signal modalities. In practice, more than 30 data converters are required in designing a mobile system in which the data-converting blocks become among the most power-hungry components in battery-operated systems. Due to the increased variety of sensors, mobile systems are meant to face several obstacles. For example, the increased number of sensors increase system power consumption during the system operation. The increased power consumption directly affects operation time because mobile systems are powered by a limited energy source. Moreover, an increased amount of information also gives rise to bandwidth problems in communication due to the increased volume of data transmission. Also, this system design requires a larger area in a silicon die so that multiple signal paths can be placed without cross-channel interference. Therefore, the system design has presented a challenge in terms of trying to resolve the design constraints such as power consumption, bandwidth usage, storage space, and design complexity issues. To overcome these obstacles, in this dissertation, efficient data acquisition and processing methods are investigated. Specifically, this thesis considers the problems of energy-efficient sampling and binary event detection. This dissertation begins by presenting a new signal sampling scheme that enables higher precision signal conversion in compressed-sensing-based signal acquisition. The proposed scheme is based on the popular successive approximation register and employs a modified compressive sensing technique to increase the resolution of successive-approximation-register (SAR) analog-to-digital converter (ADC) architecture. Circuit-level architecture is discussed to implement the proposed scheme using the SAR ADC architecture. A non-uniform quantization scheme is proposed and it improves data quality after data acquisition. The proposed scheme is expected to be used for medium- or high- frequency data conversion. Secondly, the possibility of using fewer ADCs than channels is studied by leveraging sparse-signal representation and blind-source-separation (BSS) techniques. In particular, this dissertation examines the problem of using a single ADC or quantizer system for digitizing multi-channel inputs. Mixing and de-mixing strategies are extensively studied for sampling frequency-sparse signals and the proposed multi-channel architecture can be easily implemented using today's analog/mixed-signal circuits. The third part of this dissertation investigates a binary hypothesis testing problem. In mobile devices such as smartphones and tablet PCs, a major portion of energy is consumed in user interfaces (LCD display and touch input processing). For accurate detection and better user interface, energy-efficient sensing and detection schemes are necessary to manage multiple sensor inputs. A highly efficient detection scheme is presented that can detect binary events reliably with a fraction of the energy consumption required in the conventional energy detection.Electrical and Computer Engineerin

Fully-passive switched-capacitor techniques for high performance SAR ADC design

In recent years, SAR ADC becomes more and more popular in various low-power applications such as wireless sensors and low energy radios due to its circuit simplicity, high power efficiency, and scaling compatibility. However, its speed is limited by its successive approximation procedures and its power efficiency greatly reduces with the ADC resolution going beyond 10 bit. To address these issues, this thesis proposes to embed two techniques: 1) compressive sensing (CS) and 2) noise shaping (NS) to a conventional SAR ADC. The realization of both techniques are based on fully-passive switched-capacitor techniques. CS is a recently emerging sampling paradigm, stating that the sparsity of a signal can be exploited to reduce the ADC sampling rate below the Nyquist rate. Different from conventional CS frameworks which require dedicated analog CS encoders, this thesis proposes a fully-passive CS-SAR ADC architecture which only requires minor modification to a conventional SAR ADC. Two chips are fabricated in a 0.13 µm process to prove the concept. One chip is a single-channel CS-SAR ADC which can reduce the ADC conversion rate by 4 times, thus reducing the ADC power by 4 times. In many wireless sensing applications, multiple ADCs are commonly required to sense multi-channel signals such as multi-lead ECG sensing and parallel neural recording. Therefore, the other chip is a multi-channel CS-SAR ADC which can simultaneously convert 4-channel signals with a sampling rate of one channel’s Nyquist rate. At 0.8 V and 1 MS/s, both chips achieve an effective Walden FoM of around 5 fJ/conversion-step. This thesis also proposes a novel NS SAR ADC architecture that is simple, robust and low power for high-resolution applications. Compared to conventional ∆Σ ADCs, it replaces the power-hungry active integrator with a passive integrator which only requires one switch and two capacitors. Compared to previous 1st-order NS SAR ADC works, it achieves the best NS performance and can be easily extended to 2nd-order. A 1st-order 10-bit NS SAR ADC is fabricated in a 0.13 µm process. Through NS, SNDR increases by 6 dB with OSR doubled, achieving a 12- bit ENOB at OSR = 8. An improved version of a 2nd-order 9-bit NS SAR ADC is designed and simulated in a 40 nm process. The SNDR increases by 10 dB with OSR doubled, achieving a 14-bit ENOB at OSR = 16. At a bandwidth of 312.5 kHz, the Schreier FoM is 181 dB and the Walden FoM is 12.5 fJ/conversion-step, proving that the proposed NS SAR ADC architecture can achieve high resolution and high power efficiency simultaneously.Electrical and Computer Engineerin

Design of data acquisition system for artillery unit

Data acquisition involves gathering signals that measure real world physical conditions from measurement sources and then modify it into different format for storage purpose. Typically a Data acquisition system converts physical signals which are analog in nature into digital form which is to be manipulated by a computer. In this work a multi channel data acquisition system is developed to acquire the data from Artillery unit in real time environment. More importance is given on the accuracy of the data captured and speed of operation of the developed data acquisition system. Micro controller based hardware system is developed to generate prototype signals similar to the signal generated by the artillery unit. This is required to simulate firing pulses of the artillery unit in the laboratory to test the data acquisition system off line before implementing it in the real time environment. The driver software is programmed to implement sixteen channel data acquisition system. The front end is designed in a simplified manner from the user point of view where several buttons with different nomenclature are placed for the corresponding operation of data. The capability of storage of data, retrieving the stored data in a graphical format for back analysis and instant calculation of different timing parameters during the data acquisition process made the overall system into a powerful and efficient tool. In addition to that another feature is implemented in this system where, the quest for a particular segment of stored data can be done instantly without putting any effort and necessary information can be obtained from that segment. Further analysis of stored data is done where presence of error in the signal is detected. The data gets corrupted by noise during the process of firing which makes it difficult to detect the presence of error in the signal. Hence at the outset, the signal enhancement method is implemented to the data followed by which, the error detection method is applied to find out the presence of error

Pyramic array: An FPGA based platform for many-channel audio acquisition

Array processing of audio data has many interesting applications: acoustic beamforming, source separation, indoor localization, room geometry estimation, etc. Recent advances in MEMS has produced tiny microphones, analog or even with digital converter integrated. This opens the door to create arrays with a massive number of microphones. We dub such an array many-channel by analogy to many-core processors.Microphone arrays techniques present compelling applications for robotic implementations. Those techniques can allow robots to listen to their environment and infer clues from it. Such features might enable capabilities such as natural interaction with humans, interpreting spoken commands or the localization of victims during search and rescue tasks. However, under noisy conditions robotic implementations of microphone arrays might degrade their precision when localizing sound sources. For practical applications, human hearing still leaves behind microphone arrays. Daniel Kisch is an example of how humans are able to efficiently perform echo-localization to recognize their environment, even in noisy and reverberant environments. For ubiquitous computing, another limitation of acoustic localization algorithms is within their capabilities of performing real-time Digital Signal Processing (DSP) operations. To tackle those problems, tradeoffs between size, weight, cost and power consumption compromise the design of acoustic sensors for practical applications. This work presents the design and operation of a large microphone array for DSP applications in realistic environments. To address those problems this project introduces the Pyramic sound capture system designed at LAP in EPFL. Pyramic is a custom hardware which possesses 48 microphones dis- tributed in the edges of a tetrahedron. The microphone arrays interact with a Terasic DE1-SoC board from Altera Cyclone V family devices, which combines a Hard Processor System (HPS) and a Field Programmable Gate Array (FPGA) in the same die. The HPS part integrates a dual- core ARM-based Cortex-A9 processor, which combined with the power of FPGA design suitable for processing multichannel microphone signals. This thesis explains the implementation of the Pyramic array. Moreover, FPGA-based hardware accelerators have been designed to imple- ment a Master SPI communication with the array and a parallel 48 channels FIR filters cascade of the audio data for delay-and-sum beamforming applications. Additionally, the configura- tion of the HPS part allows the Pyramic array to be controlled through a Linux based OS. The main purpose of the project is to develop a flexible platform in which real-time echo-location algorithms can be implemented. The effectiveness of the Pyramic array design is illustrated by testing the recorded data with offline direction of arrival algorithms developed at LCAV in EPFL

Timing calibration for up-converting DAC

This thesis deals with the timing error problem that appears in high frequency Digital to Analog Converters. Inequalities among signal paths in different branches and inaccuracies happened during fabrication, result in different time delays in different branches of a Digital to Analog Converter. The consequence of this inequality is having the data for different bits not arriving to the summation point at the same time. This timing error will create some glitches in the output analog signal. A new approach is introduced in this work that measures the timing error among branches of the DAC and corrects them through a calibration process. Being all the error measurement and its correction process done on chip, this approach can correct the errors created by both sources. This idea was implemented and tested in Eldo simulator. A timing error of 8pS was inserted to the MSB branch of a 10-bit binary coded DAC. After performing the calibration process on this DAC, the SFDR of the output signal was increased by about 3.2dB

A Low-Power Silicon-Photomultiplier Readout ASIC for the CALICE Analog Hadronic Calorimeter

The future e + e − collider experiments, such as the international linear collider, provide precise measurements of the heavy bosons and serve as excellent tests of the underlying fundamental physics. To reconstruct these bosons with an unprecedented resolution from their multi-jet final states, a detector system employing the particle flow approach has been proposed, requesting calorimeters with imaging capabilities. The analog hadron calorimeter based on the SiPM-on-tile technology is one of the highly granular candidates of the imaging calorimeters. To achieve the compactness, the silicon-photomultiplier (SiPM) readout electronics require a low-power monolithic solution. This thesis presents the design of such an application-specific integrated circuit (ASIC) for the charge and timing readout of the SiPMs. The ASIC provides precise charge measurement over a large dynamic range with auto-triggering and local zero-suppression functionalities. The charge and timing information are digitized using channel-wise analog-to-digital and time-to-digital converters, providing a fully integrated solution for the SiPM readout. Dedicated to the analog hadron calorimeter, the power-pulsing technique is applied to the full chip to meet the stringent power consumption requirement. This work also initializes the commissioning of the calorimeter layer with the use of the designed ASIC. An automatic calibration procedure has been developed to optimized the configuration settings for the chip. The new calorimeter base unit with the designed ASIC has been produced and its functionality has been tested