A Low-Power, Low-Area 10-Bit SAR ADC with Length-Based Capacitive DAC

A 2.5 V single-ended 10-bit successive-approximation-register analog-to-digital converter (SAR ADC) based on the TSMC 65 nm CMOS process is designed with the goal of achieving low power consumption (33.63 pJ/sample) and small area (2874 µm^2 ). It utilizes a novel length-based capacitive digital-to-analog converter (CDAC) layout to achieve low total capacitance for power efficiency, and a custom static asynchronous logic to free the dependence on a high-frequency external clock source. Two test chips have been designed and the problems found through testing the first chip are analyzed. Multiple improved versions of the ADC with minor variations are implemented on the second test chip for performance evaluation, and the test method is explained. Adviser: Sina Balkir and Michael Hoffma

A radiation-hard dual-channel 12-bit 40 MS/s ADC prototype for the ATLAS liquid argon calorimeter readout electronics upgrade at the CERN LHC

The readout electronics upgrade for the ATLAS Liquid Argon Calorimeters at the CERN Large Hadron Collider requires a radiation-hard ADC. The design of a radiation-hard dual-channel 12-bit 40 MS/s pipeline ADC for this use is presented. The design consists of two pipeline A/D channels each with four Multiplying Digital-to-Analog Converters followed by 8-bit Successive-Approximation-Register analog-to-digital converters. The custom design, fabricated in a commercial 130 nm CMOS process, shows a performance of 67.9 dB SNDR at 10 MHz for a single channel at 40 MS/s, with a latency of 87.5 ns (to first bit read out), while its total power consumption is 50 mW/channel. The chip uses two power supply voltages: 1.2 and 2.5 V. The sensitivity to single event effects during irradiation is measured and determined to meet the system requirements

Noise shaping Asynchronous SAR ADC based time to digital converter

Time-to-digital converters (TDCs) are key elements for the digitization of timing information in modern mixed-signal circuits such as digital PLLs, DLLs, ADCs, and on-chip jitter-monitoring circuits. Especially, high-resolution TDCs are increasingly employed in on-chip timing tests, such as jitter and clock skew measurements, as advanced fabrication technologies allow fine on-chip time resolutions. Its main purpose is to quantize the time interval of a pulse signal or the time interval between the rising edges of two clock signals. Similarly to ADCs, the performance of TDCs are also primarily characterized by Resolution, Sampling Rate, FOM, SNDR, Dynamic Range and DNL/INL. This work proposes and demonstrates 2nd order noise shaping Asynchronous SAR ADC based TDC architecture with highest resolution of 0.25 ps among current state of art designs with respect to post-layout simulation results. This circuit is a combination of low power/High Resolution 2nd Order Noise Shaped Asynchronous SAR ADC backend with simple Time to Amplitude converter (TAC) front-end and is implemented in 40nm CMOS technology. Additionally, special emphasis is given on the discussion on various current state of art TDC architectures.Electrical and Computer Engineerin

Capacitor Mismatch Calibration Technique to Improve the SFDR of 14-Bit SAR ADC

This paper presents mismatch calibration technique to improve the SFDR in a 14-bit successive approximation register (SAR) analog-to-digital converter (ADC) for wearable electronics application. Behavioral Monte-Carlo simulations are applied to demonstrate the effect of the proposed method where no complex digital calibration algorithm or auxiliary calibration DAC needed. Simulation results show that with a mismatch error typical of modern technology, the SFDR is enhanced by more than 20 dB with the proposed technique for a 14-bit SAR ADC

Exploiting smallest error to calibrate non-linearity in SAR ADCs

This paper presents a statistics-optimised organisation technique to achieve better element matching in Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC) in smart sensor systems. We demonstrate the proposed technique ability to achieve a significant improvement of around 23 dB on Spurious Free Dynamic Range (SFDR) of the ADC than the conventional, testing with a capacitor mismatch σu = 0.2% in a 14 bit SAR ADC system. For the static performance, the max root mean square (rms) value of differential nonlinearity (DNL) reduces from 1.63 to 0.20 LSB and the max rms value of integral nonlinearity (INL) reduces from 2.10 to 0.21 LSB. In addition, it is demonstrated that by applying grouping optimisation and strategy optimisation, the performance boosting on SFDR can be effectively achieved. Such great improvement on the resolution of the ADC only requires an off-line pre-processing digital part

A neural probe with up to 966 electrodes and up to 384 configurable channels in 0.13 μm SOI CMOS

In vivo recording of neural action-potential and local-field-potential signals requires the use of high-resolution penetrating probes. Several international initiatives to better understand the brain are driving technology efforts towards maximizing the number of recording sites while minimizing the neural probe dimensions. We designed and fabricated (0.13-μm SOI Al CMOS) a 384-channel configurable neural probe for large-scale in vivo recording of neural signals. Up to 966 selectable active electrodes were integrated along an implantable shank (70 μm wide, 10 mm long, 20 μm thick), achieving a crosstalk of −64.4 dB. The probe base (5 × 9 mm2) implements dual-band recording and a 1

LArPix: Demonstration of low-power 3D pixelated charge readout for liquid argon time projection chambers

We report the demonstration of a low-power pixelated readout system designed for three-dimensional ionization charge detection and digital readout of liquid argon time projection chambers (LArTPCs). Unambiguous 3D charge readout was achieved using a custom-designed system-on-a-chip ASIC (LArPix) to uniquely instrument each pad in a pixelated array of charge-collection pads. The LArPix ASIC, manufactured in 180 nm bulk CMOS, provides 32 channels of charge-sensitive amplification with self-triggered digitization and multiplexed readout at temperatures from 80 K to 300 K. Using an 832-channel LArPix-based readout system with 3 mm spacing between pads, we demonstrated low-noise ($<$500 e$^-$ RMS equivalent noise charge) and very low-power ($<$100 $\mu$W/channel) ionization signal detection and readout. The readout was used to successfully measure the three-dimensional ionization distributions of cosmic rays passing through a LArTPC, free from the ambiguities of existing projective techniques. The system design relies on standard printed circuit board manufacturing techniques, enabling scalable and low-cost production of large-area readout systems using common commercial facilities. This demonstration overcomes a critical technical obstacle for operation of LArTPCs in high-occupancy environments, such as the near detector site of the Deep Underground Neutrino Experiment (DUNE).Comment: 19 pages, 10 figures, 1 ancillary animation. V3 includes minor revisions based on referee comment

심전도 감시 분야를 위한 저전력 신호 특화된 축차 비교형 아날로그-디지털 변환기의 설계

학위논문 (박사)-- 서울대학교 대학원 공과대학 전기·컴퓨터공학부, 2017. 8. 김수환.Electrocardiography is an indispensable tool employed for diagnosis of cardiovascular diseases. When electrocardiograms (ECGs) need to be monitored for a long time, e.g. to diagnose arrhythmia, a device has to be worn or implanted under the skin, which requires low energy consumption. Successive approximation register analog-to-digital converters (SAR ADCs) have been especially preferred in low power applications, while the recent trend of ADC designs shows that the SAR ADCs find a much wide range of applications, and are the most versatile ADC architecture. The subject of the dissertation is the design of a signal-specific SAR ADC scheme that reduces the power consumption by exploiting the characteristics of the input signal of a particular type whose signal activity is low on average and dichotomous, as best exemplified by ECGs. This dissertation presents a 1.8-V 10-bit 1-kS/s low-power SAR ADC with the proposed signal-specific switching algorithm. The proposed adaptive switching algorithm has two operation modes suitable for the dichotomous activity of the ECG: full switching mode that resolves the full range of the input as an ordinary SAR ADC, and reduced switching mode that assumes 5 MSBs will not change and samples just the rest LSB portion and resolves it in 5 bitcycles. The reduced number of bitcycles yields saving in switching power consumption. For smooth mode change adaptive to the input signal activity, an additional function in each mode, viz., MSBs tracking in full switching mode and LSBs extrapolation in reduced switching mode, runs concurrently with the respective main operation. A behavioral model of the proposed SAR ADC with the segmented capacitor digital-to-analog converter (CDAC) topology was created in MATLAB and was used in the tests, which verified the function and effectiveness of the adaptive switching algorithm. The model describes the evolution of all internal node voltages in the CDAC by each switching action, from which the charge variation in each capacitor and the switching energy consumption can be computed. The model was extensively used for the development and analysis of the idea. The 5-bit size of the MSB section was determined from the simulation results with the behavioral model. A prototype chip was fabricated in 0.18-μm CMOS technology. Measurements with an ECG type input proved the suitability of the adaptive switching for ECG monitoring. The power reduction by the adaptive switching in each of comparator, logic, and DAC power domains was calculated from the measurements of both cases of the adaptive-switching and fixed-full-switching operations, the latter of which is equivalent to the conventional SAR ADC operation. It achieved a reduction in comparator power consumption by 39%. The DAC power, i.e. the switching power consumed in the CDAC, achieved a reduction by 1.28 nW, which is close to the result of the behavioral model simulation. The reduction in the logic power domain was 12%. In terms of total power consumption, the adaptive switching consumed 91.02 nW while the fixed full switching consumed 107.51 nW. The reduction corresponds to 15.3% in proportion. In addition, the intrinsic performance of the ADC was measured using a sinusoidal input. It achieved a signal-to-noise-and-distortion ratio of 56.24 dB and a spurious-free dynamic range of 62.00 dB. The maximum differential nonlinearity of +0.39/−1 LSBs and maximum integral nonlinearity of +0.86/−1.5 LSBs were measured. The main source of the nonlinearity is the capacitor mismatch in the CDAC.심전도는 심혈관계 질환의 진단을 위한 중요한 자료로서 감시 및 기록된다. 때로 부정맥 진단 등을 위하여 심전도를 오랜 시간 관찰해야 할 경우, 착용 가능한(웨어러블) 장비나 체내에 이식할 수 있는 장비를 사용해야 하는데, 이들은 전력 소비가 적어야 한다. 축차 비교형 아날로그-디지털 변환기(SAR ADC)는 저전력 응용 분야에서 주로 선호한 구조였으나 최근 아날로그-디지털 변환기 설계의 추세는 SAR ADC가 훨씬 넓은 응용 분야에 적용 가능하며 가장 넓은 범용성을 가진 구조임을 보여준다. 본 논문의 주제는 심전도 신호처럼 양분된 신호 활성도를 가지면서 평균 신호 활성도는 낮은 유형의 신호를 대상으로, 이 특성을 이용하여 전력의 소비를 낮추는 신호 특화된 스위칭 기법을 적용한 SAR ADC 설계이다. 본 논문에서는 신호 특화된 기법을 적용한 1.8V, 10 bit, 1kS/s의 저전력 SAR ADC 설계를 제시한다. 제안하는 적응형 스위칭 기법은 ECG의 양분된 신호 활성도 특성에 맞추어, 일반적인 SAR ADC처럼 입력의 전체 범위를 처리하는 full switching mode와, 5-bit MSB code가 변하지 않을 것이라는 가정하에 나머지 LSB 부분만 샘플링하고 처리하는 reduced switching mode의 두 가지 동작 모드를 가진다. 입력 신호 활성도에 따라 유연하게 동작 모드를 전환하기 위하여, full switching mode는 MSBs tracking, reduced switching mode는 LSBs extrapolation라는 부가 기능이 각 모드의 주 기능과 함께 동작한다. 제안한 SAR ADC의 behavioral model을 MATLAB에서 만들었고, 이를 이용한 여러 테스트에서 적응형 스위칭 기법의 기능과 효과를 검증하였다. 이 behavioral model은 SAR ADC 내에 있는 segmented CDAC의 모든 내부 node 전압의 변화를 개별 스위칭 동작에 대해 기술하므로, 이를 이용하여 각 캐패시터에 저장된 전하의 변화량이나 스위칭 에너지 소비량을 계산할 수 있다. 이 model을 idea 개발 및 분석에 광범위하게 이용하였다. 0.18μm CMOS 공정에서 시제품 칩을 제작하였다. 심전도 유형의 입력 신호를 이용한 측정을 통해 제안한 적응형 스위칭 기법이 심전도 감시 분야에 적합함을 증명하였다. 제안한 기법으로 얻어지는 ADC의 전력 감소는 제안한 적응형 스위칭으로 동작한 경우와 full switching mode로 고정된 경우(기존의 SAR ADC 동작에 해당)에서 비교기, 논리 회로, DAC 3개 영역의 전력 측정값에서 계산하였다. 비교기 회로의 전력 소비는 39% 줄었다. DAC에서 소비된 전력, 즉 CDAC의 switching 전력 소비량은 1.28 nW가 감소했는데, behavioral model의 simulation 결과와 비슷한 값이다. 논리 회로 영역에서는 12%가 줄었다. 전체 전력 소비는 적응형 스위칭 기법을 적용했을 때 91.02 nW, full switching mode로 고정했을 때 107.51 nW으로 15.3% 감소하였다. 또, sine 입력을 이용하여 설계한 ADC의 기본 성능을 측정하였다. 그 결과 56.24dB의 SNDR과 62.00 dB의 SFDR을 얻었고, 비선형성 지표인 최대 DNL과 INL은 각각 +0.39/−1 LSBs와 +0.86/−1.5 LSBs 을 얻었다. 이 비선형성 특성은 주로 CDAC 내의 캐패시터 미스매치에 기인한 것이다.Chapter 1 Introduction 1 1.1 Electrocardiography 1 1.2 Recent Trends in SAR ADC Designs 4 1.3 Dissertation Contributions and Organization 7 Chapter 2 SAR ADC Operation and Design Issues 9 2.1 Operation Principle 9 2.2 Switching Algorithms for Power Reduction 12 2.2.1 Computation of Switching Energy Consumption 12 2.2.2 Conventional Charge-Redistribution Switching 15 2.2.3 Split-Capacitor Switching 16 2.2.4 Energy-Saving Switching 18 2.2.5 Set-and-Down Switching 21 2.2.6 Merged-Capacitor Switching 22 2.3 Offset and Noise 25 2.4 Linearity 29 2.5 Area 32 Chapter 3 Adaptive Switching SAR ADC for ECG Monitoring Applications 34 3.1 ECG Characteristics and Readout Circuit 34 3.1.1 ECG Signals and Characteristics 34 3.1.2 ECG Readout Circuit 35 3.2 Related Signal-Specific Works 37 3.2.1 SAR ADC with a Bypass Window for Neural Signals 37 3.2.2 LSB-First Successive Approximation 39 3.3 Adaptive Switching 41 3.3.1 Motivation 41 3.3.2 Preliminary Test 42 3.3.3 Algorithm 46 3.3.4 Energy Consumption of SAR ADC with Segmented CDAC 54 3.3.5 Behavioral Model Simulations 59 3.3.6 Consideration on Other Applications 75 3.4 Circuit Implementation 76 3.4.1 Overview 76 3.4.2 Comparator and CDAC 78 3.4.3 Adaptive Switching Logic 81 Chapter 4 Prototype Measurements 86 4.1 Fabrication and Experiment Setup 86 4.2 Measurements 88 4.2.1 Power Reduction Measurement with ECG-Type Input 88 4.2.2 Intrinsic Performance Measurement with Sinusoidal Input 93 4.2.3 Summary of the Measurements and Specifications 96 Chapter 5 Conclusion 98 Bibliography 101 Abstract in Korean 107Docto