A 2-MS/s, 11.22 ENOB, extended input range SAR ADC with improved DNL and offset calculation

A 12-bit successive approximation register analog-to-digital converter (ADC) with extended input range is presented. Employing an input sampling scaling technique, the presented ADC can digitize the signals with an input range of 3.2 V pp-d (±1.33 V REF ). The circuit also includes a comparator offset compensation technique that results in a residual offset of less than 0.5 LSB. The chip has been designed and implemented in a 0.13-μm CMOS process and demonstrates the state-of-the-art performance, featuring an SNDR of 69.3 dB and the SFDR of 79 dB without requiring any calibration. Total power consumption of the ADC is 0.9 mW, with a measured differential non-linearity of 1.2/-1.0 LSB and INL of 2.3/-2.2 LSB

A 2-MS/s, 11.22 ENOB, extended input range SAR ADC with improved DNL and offset calculation

A 12-bit successive approximation register analog-to-digital converter (ADC) with extended input range is presented. Employing an input sampling scaling technique, the presented ADC can digitize the signals with an input range of 3.2 ± pp-d (pm 1.33~V{REF}). The circuit also includes a comparator offset compensation technique that results in a residual offset of less than 0.5 LSB. The chip has been designed and implemented in a 0.13-μ m CMOS process and demonstrates the state-of-the-art performance, featuring an SNDR of 69.3 dB and the SFDR of 79 dB without requiring any calibration. Total power consumption of the ADC is 0.9 mW, with a measured differential non-linearity of 1.2/-1.0 LSB and INL of 2.3/-2.2 LSB

A 2-MS/s, 11.22 ENOB, extended input range SAR ADC with improved DNL and offset calculation

A 12-bit successive approximation register analog-to-digital converter (ADC) with extended input range is presented. Employing an input sampling scaling technique, the presented ADC can digitize the signals with an input range of 3.2 V pp-d (±1.33 V REF ). The circuit also includes a comparator offset compensation technique that results in a residual offset of less than 0.5 LSB. The chip has been designed and implemented in a 0.13-μm CMOS process and demonstrates the state-of-the-art performance, featuring an SNDR of 69.3 dB and the SFDR of 79 dB without requiring any calibration. Total power consumption of the ADC is 0.9 mW, with a measured differential non-linearity of 1.2/-1.0 LSB and INL of 2.3/-2.2 LSB