A 14-bit 250 MS/s IF Sampling Pipelined ADC in 180 nm CMOS Process

This paper presents a 14-bit 250 MS/s ADC fabricated in a 180 nm CMOS process, which aims at optimizing its linearity, operating speed, and power efficiency. The implemented ADC employs an improved SHA with parasitic optimized bootstrapped switches to achieve high sampling linearity over a wide input frequency range. It also explores a dedicated foreground calibration to correct the capacitor mismatches and the gain error of residue amplifier, where a novel configuration scheme with little cost for analog front-end is developed. Moreover, a partial non-overlapping clock scheme associated with a high-speed reference buffer and fast comparators is proposed to maximize the residue settling time. The implemented ADC is measured under different input frequencies with a sampling rate of 250 MS/s and it consumes 300 mW from a 1.8 V supply. For 30 MHz input, the measured SFDR and SNDR of the ADC is 94.7 dB and 68.5 dB, which can remain over 84.3 dB and 65.4 dB for up to 400 MHz. The measured DNL and INL after calibration are optimized to 0.15 LSB and 1.00 LSB, respectively, while the Walden FOM at Nyquist frequency is 0.57 pJ/step

Improving Accuracy and Energy Efficiency of Pipeline Analog to Digital Converters

Analog-to-Digital converters (ADC) are key building blocks of analog and mixed-signal processing that link the natural world of analog signals and the world of digital processing. This work describes the analysis, design, development and test of novel high-resolution (≥12-bit), moderate speed (10-100MS/s), energy-efficient ADCs. Such ADCs are typically used for communication, imaging and video applications. CMOS process scaling is typically aimed at enabling fast, low-power digital circuits. Scaling leads to lower supply voltages, and to short channel devices with low gain and poor matching between small devices. On the other hand, to process and amplify analog signals analog circuits rely on wide signal swing, large transistor gain and good component matching. Hence, analog circuit performance has lagged far behind digital performance. Analog circuits such as ADCs are therefore nowadays performance bottlenecks in many electronic systems. The pipeline ADC is a popular architecture for implementing ADCs with a wide range of speed and resolution. This work aims to improve the accuracy and energy efficiency of the pipeline architecture by combining it with more accurate or more energy efficient architectures such as Sigma-Delta and Successive-Approximation (SAR). Such novel, hybrid architectures are investigated in this work. In the first design, a new architecture is developed which combines a low-OSR resetting Sigma-Delta modulator architecture with the pipeline architecture. This architecture enhances the accuracy and energy efficiency of the pipeline architecture. A prototype 14-bit 23MS/s ADC, based on this new architecture, is designed and tested. This ADC achieves calibration-free 14-bit linearity, 11.7-bit ENOB and 87dB SFDR while dissipating only 48mW of power. In the second design, new hybrid architecture based on SAR and pipeline architecture is developed. This architecture significantly improves the energy efficiency of the pipeline architecture. A prototype 12-bit 50MS/s ADC is designed based on this new architecture. “Half-gain” and “half-reference” pipeline stages are also introduced in this prototype for the first time to further reduce power dissipation. This ADC dissipates only 3.5mW power.Ph.D.Electrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/76025/1/leechun_1.pd

Time interleaved counter analog to digital converters

The work explores extending time interleaving in A/D converters, by applying a high-level of parallelism to one of the slowest and simplest types of data-converters, the counter ADC. The motivation for the work is to realise high-performance re-configurable A/D converters for use in multi-standard and multi-PHY communication receivers with signal bandwidths in the 10s to 100s of MHz. The counter ADC requires only a comparator, a ramp signal, and a digital counter, where the comparator compares the sampled input against all possible quantisation levels sequentially. This work explores arranging counter ADCs in large time-interleaved arrays, building a Time Interleaved Counter (TIC) ADC. The key to realising a TIC ADC is distributed sampling and a global multi-phase ramp generator realised with a novel figure-of-8 rotating resistor ring. Furthermore Counter ADCs allow for re-configurability between effective sampling rate and resolution due to their sequential comparison of reference levels in conversion. A prototype TIC ADC of 128-channels was fabricated and measured in 0.13μm CMOS technology, where the same block can be configured to operate as a 7-bit 1GS/s, 8-bit 500MS/s, or 9-bit 250MS/s dataconverter. The ADC achieves a sub 400fJ/step FOM in all modes of configuration

Digital Background Self-Calibration Technique for Compensating Transition Offsets in Reference-less Flash ADCs

This Dissertation focusses on proving that background calibration using adaptive algorithms are low-cost, stable and effective methods for obtaining high accuracy in flash A/D converters. An integrated reference-less 3-bit flash ADC circuit has been successfully designed and taped out in UMC 180 nm CMOS technology in order to prove the efficiency of our proposed background calibration. References for ADC transitions have been virtually implemented built-in in the comparators dynamic-latch topology by a controlled mismatch added to each comparator input front-end. An external very simple DAC block (calibration bank) allows control the quantity of mismatch added in each comparator front-end and, therefore, compensate the offset of its effective transition with respect to the nominal value. In order to assist to the estimation of the offset of the prototype comparators, an auxiliary A/D converter with higher resolution and lower conversion speed than the flash ADC is used: a 6-bit capacitive-DAC SAR type. Special care in synchronization of analogue sampling instant in both ADCs has been taken into account. In this thesis, a criterion to identify the optimum parameters of the flash ADC design with adaptive background calibration has been set. With this criterion, the best choice for dynamic latch architecture, calibration bank resolution and flash ADC resolution are selected. The performance of the calibration algorithm have been tested, providing great programmability to the digital processor that implements the algorithm, allowing to choose the algorithm limits, accuracy and quantization errors in the arithmetic. Further, systematic controlled offset can be forced in the comparators of the flash ADC in order to have a more exhaustive test of calibration

Energy and area efficient techniques for data converters

Data converters are ubiquitous building blocks of a signal chain. The rapid increase in communication and connectivity devices presents new avenues for pushing the state of the art analog to digital converters. Techniques for improving resolution, bandwidth, linearity and bit-error rate, while reducing the power, energy and area is the motivation for this research. This research focuses on achieving this goal by enabling circuit techniques, architecture techniques and calibration methods. The following techniques are proposed for enabling power, area and energy efficient analog to digital converter techniques. 1. A capacitor switching scheme for successive approximation ADC is introduced to enable 93.4% energy reduction and 75 % reduction in capacitor area as compared to a conventional SAR ADCs. 2. Asynchronous correlated level shifting technique for improving current source linearity and power supply rejection ratio of zero crossing based circuits is proposed. This technique enables asynchronous ADC architectures for energy efficient system. 3. Unified gain enhancement model is proposed to catalogue gain enhancement techniques. Class-A+ and Replicated Parallel Gain Enhancement (RPGe) amplifiers are introduced as parallel gain enhancement techniques for switched capacitor circuits. A prototype pipelined ADC using RPGE amplifier achieves 74.9 dB SNDR, 90.8 dB SFDR, 87 dB THD at 20 MS/s. Built in 1P4M 0.18 μm technology and operating at 1.3 V supply, the ADC consumes 5.9 mW. The ADC occupies 3.06 sq. mm and has a figure of merit of 65 fJ /conversion step. Extracted simulation results of the prototype pipeline ADC using dynamic RPGE amplifier achieve 74 dB SNDR, 90 dB SFDR, and 85 dB THD at 30 MS /s in a 0.18 μm process. The ADC consumes 6.6 mW from a 1.3 V supply and achieves a figure of merit of 40 fJ/C-S. 4. A low-gain amplifier based V-T converter is utilized along with a TDC to replace the function of flash ADC and the DAC references in a pipeline ADC. The simulated/ extracted performance of the chip is 12bit, 100 MHz in 65nm process while consuming approximately 8-9 mA from 1 V supply. 5. A measurement technique for detecting and correcting bit-error rate in ADCs is proposed. This multi-path ADC technique squares the bit-error rate of the ADC without consuming additional analog power. The area increase is negligible compared to the conventional modular redundancy techniques. This technique can be applied to digitally detect and correct single event transients for ADCs. A three-path ADC can restore the ADC performance independent of the input frequency and number of errors in a single path. 6. LMS algorithm is used to estimate the VCO non-linearity by using the VCO as a Nyquist ADC and utilizing a slow but accurate ADC. The simulated ADC performance improves from 5 bits to 7.8 bits by using a second order fit to the VCO non-linearity

High performance zero-crossing based pipelined analog-to-digital converters

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2011.This electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections.Cataloged from student submitted PDF version of thesis.Includes bibliographical references (p. 133-137).As CMOS processes continue to scale to smaller dimensions, the increased fT of the devices and smaller parasitic capacitance allow for more power ecient and faster digital circuits to be made. But at the same time, output impedance of transistors has gone down, as have the power supply voltages, and leakage currents have increased. These changes in the technology have made analog design more difficult. More specifically, the design of a high gain op-amp, a fundamental analog building block, has become more difficult in scaled processes. In this work, op-amps in pipelined ADCs are replaced with zero-crossing detectors(ZCD). Without the closed-loop feedback provided by the op-amp, a new set of design constraints for Zero-Crossing Based Circuits (ZCBC) is explored.by Yue Jack Chu.Ph.D

Calibration techniques in nyquist A/D converters

In modern systems signal processing is performed in the digital domain. Contrary to analog circuits, digital signal processing offers more robustness, programmability, error correction and storage possibility. The trend to shift the A/D converter towards the input of the system requires A/D converters with more dynamic range and higher sampling speeds. This puts extreme demands on the A/D converter and potentially increases the power consumption. Calibration Techniques in Nyquist A/D Converters analyses different A/D-converter architectures with an emphasis on the maximum achievable power efficiency. It is shown that in order to achieve high speed and high accuracy at high power efficiency, calibration is required. Calibration reduces the overall power consumption by using the available digital processing capability to relax the demands on critical power hungry analog components. Several calibration techniques are analyzed. The calibration techniques presented in this book are applicable to other analog-to-digital systems, such as those applied in integrated receivers. Further refinements will allow using analog components with less accuracy, which will then be compensated by digital signal processing. The presented methods allow implementing this without introducing a speed or power penalty

Digitally Assisted ADCS.

This work involves the development of digital calibration techniques for Analogto- Digital Converters. According to the 2001 International Technology Roadmap for Semiconductors, improved ADC technology is a key factor in the development of present and future applications. The switched-capacitor (SC) pipeline technique is the most popular method of implementing moderate resolution ADCs. However the advantages of CMOS, which originally made SC circuits feasible, are being eroding by process scaling. Good switches and opamps are becoming increasingly difficult to design and the growing gate leakage of deep submicron MOSFETs is causing difficulty. Traditional ADC schemes do not work well with supply voltages of 1.8V and below. Furthermore, the performance required by present and future wireless and IT applications will not be met by the present day ADC circuits techniques. Bearing in mind the challenges associated with deep sub-micron analog circuitry a new calibration technique for folding ADCs has been developed. Since digital circuitry scales well, this calibration relies heavily on digital techniques. Hence it reduces the amount of analog design involved. As this folding ADC is dominated, in terms of both functionality and power, by digital circuitry, the performance of folding will improve when implemented in smaller geometry processes. An 8-bit, 500MS/s, digitally calibrated folding ADC was designed in TSMC 0.18mm. A second prototype, 9-bit 400MS/s, was designed in ST 90nm. This ADC uses novel folders to reduce thermal noise. The major accomplishments of this work are: · The creation of a new folding ADC architecture that is digitally dominated allowing large transistor mismatch to be tolerated so that small devices can be utilized in the signal path. · The development of modeling techniques, to investigate and analyze the effects of transistor mismatch, folder linearity and redundancy in ADCs. · The design of a new folder circuit topology that decreases the required power consumption for a given noise budget. · The design of a resistor ladder DAC that uses a unique resistor layout to allow any shape ladder to be designed.Ph.D.Electrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/58426/1/ibogue_1.pd

Design Techniques for High-Performance SAR A/D Converters

The design of electronics needs to account for the non-ideal characteristics of the device technologies used to realize practical circuits. This is particularly important in mixed analog-digital design since the best device technologies are very different for digital compared to analog circuits. One solution for this problem is to use a calibration correction approach to remove the errors introduced by devices, but this adds complexity and power dissipation, as well as reducing operation speed, and so must be optimised. This thesis addresses such an approach to improve the performance of certain types of analog-to-digital converter (ADC) used in advanced telecommunications, where speed, accuracy and power dissipation currently limit applications. The thesis specifically focuses on the design of compensation circuits for use in successive approximation register (SAR) ADCs. ADCs are crucial building blocks in communication systems, in general, and for mobile networks, in particular. The recently launched fifth generation of mobile networks (5G) has required new ADC circuit techniques to meet the higher speed and lower power dissipation requirements for 5G technology. The SAR has become one of the most favoured architectures for designing high-performance ADCs, but the successive nature of the circuit operation makes it difficult to reach ∼GS/s sampling rates at reasonable power consumption. Here, two calibration techniques for high-performance SAR ADCs are presented. The first uses an on-chip stochastic-based mismatch calibration technique that is able to accurately compute and compensate for the mismatch of a capacitive DAC in a SAR ADC. The stochastic nature of the proposed calibration method enables determination of the mismatch of the CAPDAC with a resolution much better than that of the DAC. This allows the unit capacitor to scale down to as low as 280aF for a 9-bit DAC. Since the CAP-DAC causes a large part of the overall dynamic power consumption and directly determines both the sizes of the driving and sampling switches and the size of the input capacitive load of the ADC and the kT/C noise power, a small CAP-DAC helps the power efficiency. To validate the proposed calibration idea, a 10-bit asynchronous SAR ADC was fabricated in 28-nm CMOS. Measurement results show that the proposed stochastic calibration improves the ADC’s SFDR and SNDR by 14.9 dB, 11.5 dB, respectively. After calibration, the fabricated SAR ADC achieves an ENOB of 9.14 bit at a sampling rate of 85 MS/s, resulting in a Walden FoM of 10.9 fJ/c-s. The second calibration technique is a timing-skew calibration for a time-interleaved (TI) SAR ADC that calibrates/computes the inter-channel timing and offset mismatch simultaneously. Simulation results show the effectiveness of this calibration method. When used together, the proposed mismatch calibration technique and the timing-skew calibration technique enables a TI SAR ADC to be designed that can achieve a sampling rate of ∼GS/s with 10-bit resolution and a power consumption as low as ∼10mW; specifications that satisfy the requirements of 5G technology