820 research outputs found
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Noise shaping Asynchronous SAR ADC based time to digital converter
Time-to-digital converters (TDCs) are key elements for the digitization of timing information in modern mixed-signal circuits such as digital PLLs, DLLs, ADCs, and on-chip jitter-monitoring circuits. Especially, high-resolution TDCs are increasingly employed in on-chip timing tests, such as jitter and clock skew measurements, as advanced fabrication technologies allow fine on-chip time resolutions. Its main purpose is to quantize the time interval of a pulse signal or the time interval between the rising edges of two clock signals. Similarly to ADCs, the performance of TDCs are also primarily characterized by Resolution, Sampling Rate, FOM, SNDR, Dynamic Range and DNL/INL. This work proposes and demonstrates 2nd order noise shaping Asynchronous SAR ADC based TDC architecture with highest resolution of 0.25 ps among current state of art designs with respect to post-layout simulation results. This circuit is a combination of low power/High Resolution 2nd Order Noise Shaped Asynchronous SAR ADC backend with simple Time to Amplitude converter (TAC) front-end and is implemented in 40nm CMOS technology. Additionally, special emphasis is given on the discussion on various current state of art TDC architectures.Electrical and Computer Engineerin
A Resolution-Reconfigurable 5-to-10-Bit 0.4-to-1 V Power Scalable SAR ADC for Sensor Applications
A power-scalable SAR ADC for sensor applications is presented. The ADC features a reconfigurable 5-to-10-bit DAC whose power scales exponentially with resolution. At low resolutions where noise and linearity requirements are reduced, supply voltage scaling is leveraged to further reduce the energy-per-conversion. The ADC operates up to 2 MS/s at 1 V and 5 kS/s at 0.4 V, and its power scales linearly with sample rate down to leakage levels of 53 nW at 1 V and 4 nW at 0.4 V. Leakage power-gating during a SLEEP mode in between conversions reduces total power by up to 14% at sample rates below 1 kS/s. Prototyped in a low-power 65 nm CMOS process, the ADC in 10-bit mode achieves an INL and DNL of 0.57 LSB and 0.58 LSB respectively at 0.6 V, and the Nyquist SNDR and SFDR are 55 dB and 69 dB respectively at 0.55 V and 20 kS/s. The ADC achieves an optimal FOM of 22.4 fJ/conversion-step at 0.55 V in 10-bit mode. The combined techniques of DAC resolution and voltage scaling maximize efficiency at low resolutions, resulting in an FOM that increases by only 7x over the 5-bit scaling range, improving upon a 32x degradation that would otherwise arise from truncation of bits from an ADC of fixed resolution and voltage.United States. Defense Advanced Research Projects AgencyNatural Sciences and Engineering Research Council of Canad
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Design techniques for low-power SAR ADCs in nano-scale CMOS technologies
This thesis presents low power design techniques for successive approximation register (SAR) analog-to-digital converters (ADCs) in nano-scale CMOS technologies. Low power SAR ADCs face two major challenges especially at high resolutions: (1) increased comparator power to suppress the noise, and (2) increased DAC switching energy due to the large DAC size. To improve the comparatorâs power efficiency, a statistical estimation based comparator noise reduction technique is presented. It allows a low power and noisy comparator to achieve high signal-to-noise ratio (SNR) by estimating the conversion residue. A first prototype ADC in 65nm CMOS has been developed to validate the proposed noise reduction technique. It achieves 4.5 fJ/conv-step Walden figure of merit and 64.5 dB signal-to-noise and distortion ratio (SNDR). In addition, a bidirectional single-side switching technique is developed to reduce the DAC switching power. It can reduce the DAC switching power and the total number of unit capacitors by 86% and 75%, respectively. A second prototype ADC with the proposed switching technique is designed and fabricated in 180nm CMOS technology. It achieves an SNDR of 63.4 dB and consumes only 24 Wat 1MS/s, leading to aWalden figure of merit of 19.9 fJ/conv-step. This thesis also presents an improved loop-unrolled SAR ADC, which works at high frequency with reduced SAR logic power and delay. It employs the bidirectional single-side switching technique to reduce the comparator common-mode voltage variation. In addition, it uses a Vcm-adaptive offset calibration technique which can accurately calibrate comparatorâs offset at its operating Vcm. A prototype ADC designed in 40nm CMOS achieves 35 dB at 700 MS/s sampling rate and consumes only 0.95 mW, leading to a Walden figure of merit of 30 fJ/conv-step.Electrical and Computer Engineerin
Low-Power SAR ADCs:Basic Techniques and Trends
With the advent of small, battery-powered devices, power efficiency has become of paramount importance. For analog-to-digital converters (ADCs), the successive approximation register (SAR) architecture plays a prominent role thanks to its ability to combine power efficiency with a simple architecture, a broad application scope, and technology portability. In this review article, the basic design challenges for low-power SAR ADCs are summarized and several design techniques are illustrated. Furthermore, the limitations of SAR ADCs are outlined and hybrid architecture trends, such as noise-shaping SAR ADCs and pipelined SAR ADCs, are briefly introduced and clarified with examples
Energy Efficient Pipeline ADCs Using Ring Amplifiers
Pipeline ADCs require accurate amplification. Traditionally, an operational transconductance amplifier (OTA) configured as a switched-capacitor (SC) amplifier performs such amplification. However, traditional OTAs limit the power efficiency of ADCs since they require high quiescent current for slewing and bandwidth. In addition, it is difficult to design low-voltage OTAs in modern, scaled CMOS. The ring amplifier is an energy efficient and high output swing alternative to an OTA for SC circuits which is basically a three-stage inverter amplifier stabilized in a feedback configuration. However, the conventional ring amplifier requires external biases, which makes the ring amplifier less practical when we consider process, supply voltage, and temperature (PVT) variation. In this dissertation, three types of innovative ring amplifiers are presented and verified with state-of-the-art energy efficient pipeline ADCs. These new ring amplifiers overcome the limitations of the conventional ring amplifier and further improve energy efficiency.
The first topic of this dissertation is a self-biased ring amplifier that makes the ring amplifier more practical and power efficient, while maintaining the benefits of efficient slew-based charging and an almost rail-to-rail output swing. In addition, the ring amplifiers are also used as comparators in the 1.5b sub-ADCs by utilizing the unique characteristics of the ring amplifier. This removes the need for dedicated comparators in sub-ADCs, thus further reducing the power consumption of the ADC. The prototype 10.5b 100 MS/s comparator-less pipeline ADC with the self-biased ring amplifiers has measured SNDR, SNR and SFDR of 56.6 dB (9.11b), 57.5 dB and 64.7 dB, respectively, and consumes 2.46 mW, which results in Walden Figure-of-Merit (FoM) of 46.1 fJ/ conversionâstep.
The second topic is a fully-differential ring amplifier, which solves the problems of single-ended ring amplifiers while maintaining the benefits of the single-ended ring amplifiers. This differential ring-amplifier is applied in a 13b 50 MS/s SAR-assisted pipeline ADC. Furthermore, an improved capacitive DAC switching method for the first stage SAR reduces the DAC linearity errors and switching energy. The prototype ADC achieves measured SNDR, SNR and SFDR of 70.9 dB (11.5b), 71.3 dB and 84.6 dB, respectively, and consumes 1 mW. This measured performance is equivalent to Walden and Schreier FoMs of 6.9 fJ/conversionâstep and 174.9 dB, respectively.
Finally, a four-stage fully-differential ring amplifier improves the small-signal gain to over 90 dB without compromising speed. In addition, a new auto-zero noise filtering method reduces noise without consuming additional power. This is more area efficient than the conventional auto-zero noise folding reduction technique. A systematic mismatch free SAR CDAC layout method is also presented. The prototype 15b 100 MS/s calibration-free SAR-assisted pipeline ADC using the four-stage ring amplifier achieves 73.2 dB SNDR (11.9b) and 90.4 dB SFDR with a 1.1 V supply. It consumes 2.3 mW resulting in Schreier FoM of 176.6 dB.PHDElectrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttps://deepblue.lib.umich.edu/bitstream/2027.42/138759/1/yonglim_1.pd
Implementation of a 200 MSps 12-bit SAR ADC
Analog-to-digital converters (ADCs) with high conversion frequency, often based on pipelined architectures, are used for measuring instruments, wireless communication and video applications. Successive approximation register (SAR) converters offer a compact and power efficient alternative but the conversion speed is typically designed for lower frequencies. In this thesis a low-power 12-bit 200 MSps SAR ADC based on charge redistribution was designed for a 28 nm CMOS technology. The proposed design uses an efficient SAR algorithm (merged capacitor switching procedure) to reduce power consumption due to capacitor charging by 88 % compared to a conventional design, as well as reducing the total capacitor area by half. Sampling switches were bootstrapped for increased linearity compared to simple transmission gates. Another feature of the low power design is a fully-dynamic comparator which does not require a preamplifier. Pre-layout simulations of the SAR ADC with 800 MHz input frequency shows an SNDR of 64.8 dB, corresponding to an ENOB of 10.5, and an SFDR of 75.3 dB. The total power consumption is 1.77 mW with an estimated value of 500 W for the unimplemented digital logic. Calculation of the Schreier figure-of-merit was done with an input signal at the Nyquist frequency. The simulated SNDR, SFDR and power equals 69.5 dB, 77.3 dB and 1.9 mW respectively, corresponding to a figure-of merit of 176.6 dB.FrÄn analogt till digitalt - snabba och strömsnÄla omvandlare Dagens digitala samhÀlle stÀller höga krav pÄ prestanda och effektivitet. I samarbete med Ericsson i Lund har en krets för signalomvandling utvecklats. Genom smart design uppnÄs hög hastighet och lÄg strömförbrukning som ligger i forskningens framkant. FrÄn analogt till digitalt Ett viktigt byggblock för telekommunikation och videoapplikationer Àr sÄ kallade A/D-omvandlare, som översÀtter mellan analoga signaler (till exempel ljud) och digitala signaler bestÄende av ettor och nollor. En vÀldigt effektiv metod för A/D-omvandling bygger pÄ sÄ kallad successiv approximation. Metoden innebÀr att signalen som ska omvandlas jÀmförs med en referensnivÄ, som stegvis justeras för att nÀrma sig signalens vÀrde. Till slut har man en tillrÀckligt god uppskattning av vÀrdet som ska mÀtas. Just en sÄdan omvandlare har utvecklats med höga krav pÄ hastighet och energiförbrukning. Detta gjordes genom datorsimuleringar av modeller som beskriver kretsen. ReferensnivÄn skapas ofta genom att styra ett nÀtverk som lagrar elektrisk laddning. Omvandlingens noggrannhet, eller upplösning, beror pÄ hur mÄnga nivÄer som finns tillgÀngliga det vill sÀga hur nÀra signalens vÀrde man kan komma. I den designade kretsen finns hela 4096 nivÄer! Det finns mÄnga kÀllor till osÀkerhet i systemet, bland annat hur exakta referensnivÄerna Àr och hur bra jÀmförelsen med insignalen kan göras. Eftersom dessa eventuellt kan leda till en försÀmring av omvandlingens noggrannhet mÄste alla delar i kretsen utformas med detta i Ätanke. Höga hastigheter Eftersom det krÀvs mÄnga steg för referensnivÄn att nÀrma sig signalens vÀrde Àr den maximala omvandlingshastigheten ofta begrÀnsad. Med teknikens utveckling öppnas nya möjligheter i takt med att mikrochippens enskilda komponenter blir snabbare. Modern forskning visar att omvandlare baserade pÄ successiv approximation kan uppnÄ hastigheter pÄ flera miljoner mÀtvÀrden varje sekund, vilket Àven den utvecklade kretsen klarar av. Effektiv design Nya metoder för successiv approximation möjliggör stora besparingar nÀr det gÀller effektförbrukning, till exempel genom att effektivisera upp- och urladdningen av nÀtverket. Genom smÄ Àndringar kunde nÀtverkets energiförbrukning minskas med över 90 % samtidigt som dess area halverades. Eftersom produktionskostnaden för integrerade kretsar Àr hög medför varje minskning av kretsens area att kostnaden sjunker
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Design and implementation of Radix-3/Radix-2 based novel hybrid SAR ADC in scaled CMOS technologies
This thesis focuses on low power and high speed design techniques for successive
approximation register (SAR) analog-to-digital converters (ADCs) in nanoscale
CMOS technologies. SAR ADCsâ speed is limited by the number of bits of
resolution. An N-bit conventional SAR ADC takes N conversion cycles. To speed
up the conversion process, we introduce a radix-3 SAR ADC which can compute
1:6 bits per cycle. To our knowledge, it is the first fully programmable and efficiently
hardware controlled radix-3 SAR ADC. We had to use two comparators per
cycle due to ADC architecture and we proposed a simple calibration scheme for
the comparators. Also, as the architecture of the DAC array is completely different
from the architecture of conventional radix-2 SAR ADCâs DAC arrays, we came up
with an algorithm for calibration of capacitors of the DAC.
Low power SAR ADCs face two major challenges especially at high resolutions:
(1) increased comparator power to suppress the noise, and (2) increased
DAC switching energy due to the large DAC size. Due to our proposed architecture,the radix-3 SAR ADC uses two comparators per cycle and two differential DACs.
To improve the comparatorâs power efficiency, an efficient and low cost calibration
technique has been introduced. It allows a low power and noisy comparator to
achieve high signal-to-noise ratio (SNR).
To improve the DAC switching energy, we introduced a radix-3/radix-2
based novel hybrid SAR ADC. We use two single ended DACs for radix-3 SAR
ADC and these two single ended DACs can be used as one differential DAC for
radix-2 SAR ADC. So, overall, we only have a single DAC as conventional radix-
2 SAR ADC. In addition, a monotonic switching technique is adopted for radix-2
search to reduce the DAC capacitor size and hence, to reduce switching power. It
can reduce the total number of unit capacitors by four times. Our proposed hybrid
SAR ADC can achieve less DAC energy compared to radix-3 and radix-2 SAR
ADCs. Also, to utilize technology scaling, we used the minimum capacitor size
allowed by thermal noise limitations. To achieve high resolution, we introduced
calibration algorithm for the DAC array.
As mentioned earlier, the radix-3 SAR ADC offers higher power than conventional
radix-2 SAR ADC because of simultaneous use of two comparators. In
the proposed hybrid SAR ADC, we will be using radix-3 search for first few MSB
bits. So, the resolution required for radix-3 comparators are much larger than the
LSB value of 10-bit ADC. By implementing calibration of comparators, we can
use low power, high input referred offset and high speed comparators for radix-3
search. Radix-2 search will be used for rest of the bits and the resolution of the
radix-2 comparator has to be less than the required LSB value. So, a high power, low input referred offset and high speed comparator is used for radix-2 search.
Also, we introduced clock gating for comparators. So, radix-3 comparators will not
toggle during radix-2 search and the radix-2 comparators will be inactive during
radix-3 search. By using the aforementioned techniques, the overall comparator
power is definitely less than a radix-3 SAR ADC and comparable to a conventional
radix-2 SAR ADC.
A prototype radix-3/radix-2 based hybrid SAR ADC with the proposed
technique is designed and fabricated in 40nm CMOS technology. It achieves an
SNDR of 56.9 dB and consumes only 0.38 mW power at 30MS/s, leading to a
Walden figure of merit of 21.5 fJ/conv-step.Electrical and Computer Engineerin
Study of a Time Assisted SAR ADC
The demand for low power systems has been increasing in recent years and Analogto-
Digital Converters (ADCs) are key blocks of many of these systems as they convert a
physical quantity into the digital domain so that this information can be further processed or stored using digital techniques.
Data Converters based on Charge Redistribution using of Successive Approximation
Registers (SAR) are becoming one of the most popular ADC architectures for moderate
speed, medium resolution and low power applications. Due to their low analog complexity SAR ADCs benefit from technology scaling. However, this scaling often comes with a supply voltage reduction and the noise levels do not decrease at the same rate, which translates into a performance decrease. Therefore, new opportunities emerge to explore other physical quantities such as time, frequency, phase or charge in the circuit.
This thesis focuses on studying how the time domain information can be used to
increase the performance of SAR ADCs. To do so, a new SAR ADC architecture is proposed in which a Time-to-Digital Converter (TDC) is used to convert the time domain information, provided by the comparator, into the digital domain. This new architecture was modelled in MATLAB as a 12 bit TDC assisted SAR ADC, using information from electrical simulations of the comparator and the TDC, designed in Cadence in 65 nm ST Microelectronics CMOS technology.
Simulation results demonstrated that, to achieve a better performance when compared
to more traditional SAR structures, the TDC energy and latency should be minimized.
Another limiting factor was the large voltage range in which only 1 bit could be extracted from the time-to-voltage conversion by the TDC due to the comparatorâs fast response in this range. The proposed architecture was also extended to incorporate a Bypass Window in the time domain, which allowed to substantially decrease the number of clock cycles necessary to solve the 12 bits of the ADC
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