Application of MIMO DF equalization to high-speed off-chip communication

In this contribution, we present a multiple-input multiple-output (MIMO) equalizer with decision feedback (DF) for high-speed chip-to-chip communication. We derive an elegant closed-form expression for the minimum mean square error (MMSE) equalization filters and show that the application of MIMO DF equalization (DFE) allows to significantly improve the reliability of high-speed communication over low-cost electrical interconnects

MIMO pre-equalization and DFE for high-speed off-chip communication

In this contribution, we present a multiple-input multiple-output (MIMO) transceiver scheme for high-speed chip-to-chip communication over low-cost electrical interconnects. Linear MIMO pre-equalization at the transmitter is combined with decision feedback equalization (DFE) at the receiver to counteract the adverse effect of inter symbol interference (ISI) and crosstalk (XT). Considering an energy constraint at the transmit side, we derive elegant closed-form expressions for the equalization filters under a minimum mean square error (MMSE) criterion. Numerical analysis shows that the combination of linear MIMO pre-equalization and MIMO DFE allows to significantly improve the reliability of future high-speed off-chip communication

On Partial Response Signaling for MIMO Equalization on Multi-Gbit/s Electrical Interconnects

Because of its ability to deal with intersymbol interference (ISI) and crosstalk (XT) over mutually coupled electrical interconnects, multiple-input multiple-output (MIMO) decision feedback equalization (DFE) has proven to be a promising low-cost solution for achieving multi-Gbit/s wireline communication on- and off-chip. However, not only does the channel become very sensitive to manufacturing tolerances at very high symbol rates, the latency in the feedback loop becomes prohibitively large as well. Whereas the former issue has been addressed by adopting a stochastic MIMO approach where (part of) the equalization filters depend on the channel statistics rather than on the actual channel, we tackle in this paper the latency issue by setting to zero the first N taps of the feedback filters. Moreover, we show that precoded partial response (PR) signaling can improve the performance of the resulting scheme, although the achieved gain is smaller than in the case of single-input single-output (SISO) equalization

Equalization of multi-Gb/s chip-to-chip interconnects affected by manufacturing tolerances

Electrical chip-to-chip interconnects suffer from considerable intersymbol interference at multi-Gb/s data rates, due to the frequency-dependent attenuation. Hence, reliable communication at high data rates requires equalization, to compensate for the channel response. As these interconnects are prone to manufacturing tolerances, the equalizer must be adjusted to each specific channel realization to perform optimally. We adopt a reduced-complexity equalization scheme where (part of) the equalizer is fixed, by involving the channel statistics into the equalizer derivation. For a 10 cm on-board microstrip interconnect with a 10% tolerance on its parameters, we point out that 2-PAM transmission using a fixed prefilter and an adjustable feedback filter, both with few taps, yields only a moderate bit error rate degradation, compared to the all-adjustable equalizer; at a bit error rate of 1e-12 these degradations are about 1.1  dB and 3  dB, when operating at 20 Gb/s and 80 Gb/s, respectively

Design of Energy-Efficient Equalization and Data Encoding/Decoding Techniques for Wireline Communication Systems

Ever increasing global internet data traffic has driven up the demand for cutting-edge high-speed wireline communication systems including SerDes PHY for various interfaces, interconnects, data centers servers and switches in optical systems. Operating wireline communications at higher data rates leads to signals suffering from greater channel loss and exponential increase in power consumption, mainly caused by a heavier amount of required equalization. In this dissertation, two distinct methodologies for designing SerDes transceivers are presented: 1) a pulse width modulated (PWM) time-domain feed forward equalizer (FFE) and linearity improvement technique for higher-order pulse amplitude modulation (PAM) including PAM-8, and 2) an inter-symbol interference (ISI)-resilient data encoding and decoding technique with Dicode encoding and error correction logic for low-bandwidth wireline channels, as an alternative strategy for communicating in an energy-efficient way on bandwidth-limited wireline channels without using conventional equalizers or filters. The first topic is a PAM-8 wireline transceiver with receiver-side pulse-width-modulated (PWM) or time-domain based feed forward equalization (FFE) technique. The receiver converts voltage-modulated signals or PAM signals to PWM signals and processes them using inverter based delay elements having rail to rail voltage swing. Time-to-voltage and voltage-to-time converters are designed to have non-linearity with opposite signs with the aim of achieving higher front-end linearity on the receiver. The proposed PAM-8 transceiver can operate from 12.0 Gb/s to 39.6 Gb/s and compensates 14 dB loss at 6.6 GHz with an efficiency of 8.66 pJ/bit in 65 nm CMOS. The second topic is an alternative strategy for communicating on bandwidth-limited wireline channels without using conventional equalizers or filters (FFE, DFE, and CTLE): Inter-symbol interference (ISI) resilient Dicode encoding and error correction for low-bandwidth wireline channels. The key observation is that Dicode-encoded data have no consecutive 1s or -1s. With this known information, the error correction logic at the receiver can correct multi-bit errors due to ISI. Implemented in 65 nm CMOS, the proposed digital encoding and decoding approach can achieve BER less than 10−12 while communicating on a channel with an insertion loss of 24.2 dB and 21.4 dB with 2.56 pJ/bit and 2.66 pJ/bit efficiency while operating at 13.6 Gb/s and 16 Gb/s, respectively

Optics for AI and AI for Optics

Artificial intelligence is deeply involved in our daily lives via reinforcing the digital transformation of modern economies and infrastructure. It relies on powerful computing clusters, which face bottlenecks of power consumption for both data transmission and intensive computing. Meanwhile, optics (especially optical communications, which underpin today’s telecommunications) is penetrating short-reach connections down to the chip level, thus meeting with AI technology and creating numerous opportunities. This book is about the marriage of optics and AI and how each part can benefit from the other. Optics facilitates on-chip neural networks based on fast optical computing and energy-efficient interconnects and communications. On the other hand, AI enables efficient tools to address the challenges of today’s optical communication networks, which behave in an increasingly complex manner. The book collects contributions from pioneering researchers from both academy and industry to discuss the challenges and solutions in each of the respective fields