대역 외 방해신호에 내성을 가지는 광대역 수신기에 관한 연구

학위논문 (박사)-- 서울대학교 대학원 : 공과대학 전기·컴퓨터공학부, 2018. 2. 남상욱.In this thesis, a study of wideband receivers as one of the practical SDR receiver implementations is presented. The out-of-band interference signal (or blocker), which is the biggest problem of the wideband receiver is investigated, and have studied how to effectively remove it. As a result of reviewing previous studies, we have developed a wideband receiver based on the current-mode receiver structure and attempted to eliminate the blocker. The contents of the step-by-step research are as follows. First, attention was paid to the linearity of a low-noise transconductance amplifier (LNTA), which is the base block of current-mode receivers. In current-mode receivers, the LNTA should have a high transconductance (Gm) value to achieve a low noise figure, but a high Gm value results in low linearity. To solve this trade-off, we proposed a linearization method of transconductors. The proposed technique eliminates the third-order intermodulation distortion (IMD3) in a feed-forward manner using two paths. A transconductor having a transconductance of 2Gm is disposed in the main path, and an amplifier having a gain of ∛2 and a Gm-sized transconductor are located in the auxiliary path. This structure allows for some fundamental signal loss but cancel the IMD3 component at the output. As a result, the entire transconductor circuit can have high linearity due to the removed IMD3 component. We have designed a reconfigurable high-pass filter using a linearized transconductor and have demonstrated its performance. The fabricated circuit achieved a high input-referred third-order intercept point(IIP3) performance of 19.4 dBm. Then, a further improved linearized transconductor is designed. Since the linearized transconductors have a high noise figure due to the additional circuitry used for linearization, we have proposed a more suitable form for application to LNTA through noise figure analysis. The improved LNTA is designed to operate in low noise mode when there is no blocker, and can be switched to operate in high linearity mode when the blocker exists. We also applied noise cancelling techniques to the receiver to improve the noise figure performance of the wideband receiver circuit. A feedback path has been added to the current-mode receiver structure consisting of the LNTA, the mixer and the baseband transimpedance amplifier (TIA), and the noise signal can be detected using this path. This feedback path also maintains the input matching of the receiver to 50 Ω in a wide bandwidth. By adding an auxiliary path to the receiver, the in-band signal is amplified and the detected noise is removed from the baseband. The completed circuit exhibited wideband performance from 0.025 GHz to 2 GHz and IIP3 performance of -6.9 dBm in the high linearity mode. Finally, we designed a double noise-cancelling wideband receiver circuit by improving the performance of a wideband receiver with high immunity to blocker signals. In previous receivers, the LNTA was operated in two modes depending on the situation. In the improved receiver, the Gm ratio of the linearized LNTA was changed and the RF noise-cancelling technique was applied. The input matching and noise cancelling scheme introduced in the previous circuit was also applied and a wideband receiver circuit was designed to perform double noise-cancelling. As a result, the linearization and noise-cancellation of LNTA could be achieved at the same time, and the completed receiver circuit showed high IIP3 performance of 5 dBm with minimum noise figure of 1.4 dB. In conclusion, this thesis proposed a linearization technique for transconductor circuit and designed a wideband receiver based on current-mode receiver. The designed receiver circuit experimentally verified that it has low noise figure performance and high IIP3 performance and is tolerant to out-of-band blocker signals.Chapter 1. Introduction 1 1.1. Motivation of Wideband Receiver Architecture 2 1.2. Challenges in Designing Wideband Receiver 7 1.3. Prior Researches 13 1.3.1. N-Path Filter 14 1.3.2. Feed-Forward Blocker Filtering 16 1.3.3. Current-Mode Receiver 18 1.4. Research Objectives and Thesis Organization 22 Chapter 2. Transconductor Linearization Technique and Design of Tunable High-pass Filter 24 2.1. Transconductor Linearization Technique 27 2.2. Design of Tunable High-pass Filter 36 2.3. Measurement Results 41 2.4. Conclusions 46 Chapter 3. Wideband Noise-Cancelling Receiver Front-End Using Linearized Transconductor 47 3.1. Low-Noise Transconductance Amplifier Based on Linearized Transconductor 49 3.2. Wideband Noise-Cancelling Receiver Architecture 58 3.3. Measurement Results 64 3.4. Conclusions 70 Chapter 4. Blocker-Tolerant Wideband Double Noise-Cancelling Receiver Front-End 71 4.1. Linearized Noise-Cancelling Low-Noise Transconductance Amplifier 73 4.2. Wideband Double Noise-Cancelling Receiver Front-End 83 4.3. Measurement Results 90 4.4. Conclusions 97 Chapter 5. Conclusions 98 Bibliography 102 Abstract in Korean 112Docto

Architectures and Circuit Techniques for High-Performance Field-Programmable CMOS Software Defined Radios

Next-generation wireless communication systems put more stringent performance requirements on the wireless RF receiver circuits. Sensitivity, linearity, bandwidth and power consumption are some of the most important specifications that often face tightly coupled tradeoffs between them. To increase the data throughput, a large number of fragmented spectrums are being introduced to the wireless communication standards. Carrier aggregation technology needs concurrent communication across several non-contiguous frequency bands, which results in a rapidly growing number of band combinations. Supporting all the frequency bands and their aggregation combinations increases the complexity of the RF receivers. Highly flexible software defined radio (SDR) is a promising technology to address these applications scenarios with lower complexity by relaxing the specifications of the RF filters or eliminating them. However, there are still many technology challenges with both the receiver architecture and the circuit implementations. The performance requirements of the receivers can also vary across different application scenario and RF environments. Field-programmable dynamic performance tradeoff can potentially reduce the power consumption of the receiver. In this dissertation, we address the performance enhancement challenges in the wideband SDRs by innovations at both the circuit building block level and the receiver architecture level. A series of research projects are conducted to push the state-of-the-art performance envelope and add features such as field-programmable performance tradeoff and concurrent reception. The projects originate from the concept of thermal noise canceling techniques and further enhance the RF performance and add features for more capable SDR receivers. Four generations of prototype LNA or receiver chips are designed, and each of them pushes at least one aspect of the RF performance such as bandwidth, linearity, and NF. A noise-canceling distributed LNA breaks the tradeoff between NF and RF bandwidth by introducing microwave circuit techniques from the distributed amplifiers. The LNA architecture uniquely provides ultra high bandwidth and low NF at low frequencies. A family of field-programmable LNA realized field-programmable performance tradeoff with current-reuse programmable transconductance cells. Interferer-reflecting loops can be applied around the LNAs to improve their input linearity by rejecting the out-of-band interferers with a wideband low in- put impedance. A low noise transconductance amplifier (LNTA) that operates in class-AB-C is invented to can handle rail-to-rail out-of-band blocker without saturation. Class-AB and class-C transconductors form a composite amplifier to increase the linear range of the input voltage. A new antenna interface named frequency-translational quadrature-hybrid (FTQH) breaks the input impedance matching requirement of the LNAs by introducing quadrature hybrid couplers to the CMOS RFIC design. The FTQH receiver achieves wideband sub-1dB NF and supports scalable massive frequency-agile concurrent reception

Switched-Capacitor RF Receivers for High Interferer Tolerance

The demand for broadband wireless communication is growing rapidly, requiring more spectrum resources. However, spectrum usage is inefficient today because different frequency bands are allocated for different communication standards and most of the bands are not highly occupied. Cognitive radio systems with dynamic spectrum access improve spectrum efficiency, but they require wideband tunable receiver hardware. In such a system, a preselect filter is required for the RF receiver front end, because an out-of-band (OB) interferer can block the front end or cause distortion, desensitizing the receiver. In a conventional solution, off-chip passive filters, such as surface-acoustic-wave (SAW) filters, are used to reject the OB interferer. However, such passive filters are hardly tunable, have large area, and are very expensive. On-chip, high-selectivity, linearly tunable RF filters are, therefore, a hot topic in RF front-end research. Switched-capacitor (SC) RF filters, such as N-path filters, feature good linearity and tunability, making them good candidates for tunable RF filters. However, N-path filters have some drawbacks: notably, a poor harmonic response and limited close-by blocker tolerance. This thesis presents the design and implementation of several interferer-tolerant receivers based on SC technology. We present an RF receiver with a harmonic-rejecting N-path filter to improve the harmonic response of the N-path bandpass filter. It features tunable narrowband filtering and high attenuation of the third- and fifth-order LO harmonics at the LNA output, which improves the blocker tolerance at LO harmonics. The 0.2-1 GHz RF receiver is implemented in a 65 nm CMOS process. The blocker 1 dB compression point (B1dB) is -2.4 dBm at a 20 MHz offset, and remains high at the third- and fifth-order LO harmonics. The LNA’s reverse isolation helps keep the LO emission below -90 dBm. A two-stage harmonic-rejection approach offers a > 51 dB harmonic-rejection ratio at the third- and fifth-order LO harmonics without calibration. To improve tolerance for close-by blockers, we further present an SC RF receiver achieving high-order, tunable, highly linear RF filtering. We implement RF input impedance matching, N-path filtering, high-order discrete-time infinite-impulse response (IIR) filtering and downconversion using only switches and capacitors in a 0.1-0.7 GHz prototype with tunable center frequency, programmable filter order, and very high tolerance for OB blockers. The 40 nm CMOS receiver consumes 38.5-76.5mA, achieves 40 dB gain, 24 dBm OB IIP3, 14.7 dBm B1dB for a 30MHz blocker offset, 6.8-9.7 dB noise figure, and > 66dB calibrated harmonic rejection ratio. The key drawback of our earlier SC receiver is the relatively high theoretical lower limit of the noise figure. To improve the noise performance, we developed a 0.1-0.6 GHz chopping SC RF receiver with an integrated blocker detector. We achieve RF impedance matching, high-order OB interferer filtering, and flicker-noise chopping with passive SC circuits only. The 34-80 mW 65 nm receiver achieves 35 dB gain, 4.6-9 dB NF, 31 dBm OB-IIP3, and 15 dBm B1dB. The 0.2 mW integrated blocker detector detects large OB blockers with only a 1 us response time. The filter order can be adapted to blocker power with the blocker detector

Advances in Integrated Circuit Design and Implementation for New Generation of Wireless Transceivers

User’s everyday outgrowing demand for high-data and high performance mobile devices pushes industry and researchers into more sophisticated systems to fulfill those expectations. Besides new modulation techniques and new system designs, significant improvement is required in the transceiver building blocks to handle higher data rates with reasonable power efficiency. In this research the challenges and solution to improve the performance of wireless communication transceivers is addressed. The building block that determines the efficiency and battery life of the entire mobile handset is the power amplifier. Modulations with large peak to average power ratio severely degrade efficiency in the conventional fixed-biased power amplifiers (PAs). To address this challenge, a novel PA is proposed with an adaptive load for the PA to improve efficiency. A nonlinearity cancellation technique is also proposed to improve linearity of the PA to satisfy the EVM and ACLR specifications. Ultra wide-band (UWB) systems are attractive due to their ability for high data rate, and low power consumption. In spite of the limitation assigned by the FCC, the coexistence of UWB and NB systems are still an unsolved challenge. One of the systems that is majorly affected by the UWB signal, is the 802.11a system (5 GHz Wi-Fi). A new analog solution is proposed to minimize the interference level caused by the impulse Radio UWB transmitter to nearby narrowband receivers. An efficient 400 Mpulse/s IR-UWB transmitter is implemented that generates an analog UWB pulse with in-band notch that covers the majority of the UWB spectrum. The challenge in receiver (RX) design is the over increasing out of blockers in applications such as cognitive and software defined radios, which are required to tolerate stronger out-of-band (OB) blockers. A novel RX is proposed with a shunt N-path high-Q filter at the LNA input to attenuate OB-blockers. To further improve the linearity, a novel baseband blocker filtering techniques is proposed. A new TIA has been designed to maintain the good linearity performance for blockers at large frequency offsets. As a result, a +22 dBm IIP3 with 3.5 dB NF is achieved. Another challenge in the RX design is the tough NF and linearity requirements for high performance systems such as carrier aggregation. To improve the NF, an extra gain stage is added after the LNA. An N-path high-Q band-pass filter is employed at the LNA output together with baseband blocker filtering technique to attenuate out-of-band blockers and improve the linearity. A noise-cancellation technique based on the frequency translation has been employed to improve the NF. As a result, a 1.8dB NF with +5 dBm IIP3 is achieved. In addition, a new approach has been proposed to reject out of band blockers in carrier aggregation scenarios. The proposed solution also provides carrier to carrier isolation compared to typical solution for carrier aggregation

HIGH PERFORMANCE CMOS WIDE-BAND RF FRONT-END WITH SUBTHRESHOLD OUT OF BAND SENSING

In future, the radar/satellite wireless communication devices must support multiple standards and should be designed in the form of system-on-chip (SoC) so that a significant reduction happen on cost, area, pins, and power etc. However, in such device, the design of a fully on-chip CMOS wideband receiver front-end that can process several radar/satellite signal simultaneously becomes a multifold complex problem. Further, the inherent high-power out-of-band (OB) blockers in radio spectrum will make the receiver more non-linear, even sometimes saturate the receiver. Therefore, the proper blocker rejection techniques need to be incorporated. The primary focus of this research work is the development of a CMOS high-performance low noise wideband receiver architecture with a subthreshold out of band sensing receiver. Further, the various reconfigurable mixer architectures are proposed for performance adaptability of a wideband receiver for incoming standards. Firstly, a high-performance low- noise bandwidthenhanced fully differential receiver is proposed. The receiver composed of a composite transistor pair noise canceled low noise amplifier (LNA), multi-gate-transistor (MGTR) trans-conductor amplifier, and passive switching quad followed by Tow Thomas bi-quad second order filter based tarns-impedance amplifier. An inductive degenerative technique with low-VT CMOS architecture in LNA helps to improve the bandwidth and noise figure of the receiver. The full receiver system is designed in UMC 65nm CMOS technology and measured. The packaged LNA provides a power gain 12dB (including buffer) with a 3dB bandwidth of 0.3G – 3G, noise figure of 1.8 dB having a power consumption of 18.75mW with an active area of 1.2mm*1mm. The measured receiver shows 37dB gain at 5MHz IF frequency with 1.85dB noise figure and IIP3 of +6dBm, occupies 2mm*1.2mm area with 44.5mW of power consumption. Secondly, a 3GHz-5GHz auxiliary subthreshold receiver is proposed to estimate the out of blocker power. As a redundant block in the system, the cost and power minimization of the auxiliary receiver are achieved via subthreshold circuit design techniques and implementing the design in higher technology node (180nm CMOS). The packaged auxiliary receiver gives a voltage gain of 20dB gain, the noise figure of 8.9dB noise figure, IIP3 of -10dBm and 2G-5GHz bandwidth with 3.02mW power consumption. As per the knowledge, the measured results of proposed main-high-performancereceiver and auxiliary-subthreshold-receiver are best in state of art design. Finally, the various viii reconfigurable mixers architectures are proposed to reconfigure the main-receiver performance according to the requirement of the selected communication standard. The down conversion mixers configurability are in the form of active/passive and Input (RF) and output (IF) bandwidth reconfigurability. All designs are simulated in 65nm CMOS technology. To validate the concept, the active/ passive reconfigurable mixer configuration is fabricated and measured. Measured result shows a conversion gain of 29.2 dB and 25.5 dB, noise figure of 7.7 dB and 10.2 dB, IIP3 of -11.9 dBm and 6.5 dBm in active and passive mode respectively. It consumes a power 9.24mW and 9.36mW in passive and active case with a bandwidth of 1 to 5.5 GHz and 0.5 to 5.1 GHz for active/passive case respectively

Energy-Efficient Wireless Circuits and Systems for Internet of Things

As the demand of ultra-low power (ULP) systems for internet of thing (IoT) applications has been increasing, large efforts on evolving a new computing class is actively ongoing. The evolution of the new computing class, however, faced challenges due to hard constraints on the RF systems. Significant efforts on reducing power of power-hungry wireless radios have been done. The ULP radios, however, are mostly not standard compliant which poses a challenge to wide spread adoption. Being compliant with the WiFi network protocol can maximize an ULP radio’s potential of utilization, however, this standard demands excessive power consumption of over 10mW, that is hardly compatible with in ULP systems even with heavy duty-cycling. Also, lots of efforts to minimize off-chip components in ULP IoT device have been done, however, still not enough for practical usage without a clean external reference, therefore, this limits scaling on cost and form-factor of the new computer class of IoT applications. This research is motivated by those challenges on the RF systems, and each work focuses on radio designs for IoT applications in various aspects. First, the research covers several endeavors for relieving energy constraints on RF systems by utilizing existing network protocols that eventually meets both low-active power, and widespread adoption. This includes novel approaches on 802.11 communication with articulate iterations on low-power RF systems. The research presents three prototypes as power-efficient WiFi wake-up receivers, which bridges the gap between industry standard radios and ULP IoT radios. The proposed WiFi wake-up receivers operate with low power consumption and remain compatible with the WiFi protocol by using back-channel communication. Back-channel communication embeds a signal into a WiFi compliant transmission changing the firmware in the access point, or more specifically just the data in the payload of the WiFi packet. With a specific sequence of data in the packet, the transmitter can output a signal that mimics a modulation that is more conducive for ULP receivers, such as OOK and FSK. In this work, low power mixer-first receivers, and the first fully integrated ultra-low voltage receiver are presented, that are compatible with WiFi through back-channel communication. Another main contribution of this work is in relieving the integration challenge of IoT devices by removing the need for external, or off-chip crystals and antennas. This enables a small form-factor on the order of mm3-scale, useful for medical research and ubiquitous sensing applications. A crystal-less small form factor fully integrated 60GHz transceiver with on-chip 12-channel frequency reference, and good peak gain dual-mode on-chip antenna is presented.PHDElectrical and Computer EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/162975/1/jaeim_1.pd

A Millimeter-Wave Coexistent RFIC Receiver Architecture in 0.18-µm SiGe BiCMOS for Radar and Communication Systems

Innovative circuit architectures and techniques to enhance the performance of several key BiCMOS RFIC building blocks applied in radar and wireless communication systems operating at the millimeter-wave frequencies are addressed in this dissertation. The former encapsulates the development of an advanced, low-cost and miniature millimeter-wave coexistent current mode direct conversion receiver for short-range, high-resolution radar and high data rate communication systems. A new class of broadband low power consumption active balun-LNA consisting of two common emitters amplifiers mutually coupled thru an AC stacked transformer for power saving and gain boosting. The active balun-LNA exhibits new high linearity technique using a constant gm cell transconductance independent of input-outputs variations based on equal emitters’ area ratios. A novel multi-stages active balun-LNA with innovative technique to mitigate amplitude and phase imbalances is proposed. The new multi-stages balun-LNA technique consists of distributed feed-forward averaging recycles correction for amplitude and phase errors and is insensitive to unequal paths parasitic from input to outputs. The distributed averaging recycles correction technique resolves the amplitude and phase errors residuals in a multi-iterative process. The new multi-stages balun-LNA averaging correction technique is frequency independent and can perform amplitude and phase calibrations without relying on passive lumped elements for compensation. The multi-stage balun-LNA exhibits excellent performance from 10 to 50 GHz with amplitude and phase mismatches less than 0.7 dB and 2.86º, respectively. Furthermore, the new multi-stages balun-LNA operates in current mode and shows high linearity with low power consumption. The unique balun-LNA design can operates well into mm-wave regions and is an integral block of the mm-wave radar and communication systems. The integration of several RFIC blocks constitutes the broadband millimeter-wave coexistent current mode direct conversion receiver architecture operating from 22- 44 GHz. The system and architectural level analysis provide a unique understanding into the receiver characteristics and design trade-offs. The RF front-end is based on the broadband multi-stages active balun-LNA coupled into a fully balanced passive mixer with an all-pass in-phase/quadrature phase generator. The trans-impedance amplifier converts the input signal current into a voltage gain at the outputs. Simultaneously, the high power input signal current is channelized into an anti-aliasing filter with 20 dB rejection for out of band interferers. In addition, the dissertation demonstrates a wide dynamic range system with small die area, cost effective and very low power consumption

A Millimeter-Wave Coexistent RFIC Receiver Architecture in 0.18-µm SiGe BiCMOS for Radar and Communication Systems

Innovative circuit architectures and techniques to enhance the performance of several key BiCMOS RFIC building blocks applied in radar and wireless communication systems operating at the millimeter-wave frequencies are addressed in this dissertation. The former encapsulates the development of an advanced, low-cost and miniature millimeter-wave coexistent current mode direct conversion receiver for short-range, high-resolution radar and high data rate communication systems. A new class of broadband low power consumption active balun-LNA consisting of two common emitters amplifiers mutually coupled thru an AC stacked transformer for power saving and gain boosting. The active balun-LNA exhibits new high linearity technique using a constant gm cell transconductance independent of input-outputs variations based on equal emitters’ area ratios. A novel multi-stages active balun-LNA with innovative technique to mitigate amplitude and phase imbalances is proposed. The new multi-stages balun-LNA technique consists of distributed feed-forward averaging recycles correction for amplitude and phase errors and is insensitive to unequal paths parasitic from input to outputs. The distributed averaging recycles correction technique resolves the amplitude and phase errors residuals in a multi-iterative process. The new multi-stages balun-LNA averaging correction technique is frequency independent and can perform amplitude and phase calibrations without relying on passive lumped elements for compensation. The multi-stage balun-LNA exhibits excellent performance from 10 to 50 GHz with amplitude and phase mismatches less than 0.7 dB and 2.86º, respectively. Furthermore, the new multi-stages balun-LNA operates in current mode and shows high linearity with low power consumption. The unique balun-LNA design can operates well into mm-wave regions and is an integral block of the mm-wave radar and communication systems. The integration of several RFIC blocks constitutes the broadband millimeter-wave coexistent current mode direct conversion receiver architecture operating from 22- 44 GHz. The system and architectural level analysis provide a unique understanding into the receiver characteristics and design trade-offs. The RF front-end is based on the broadband multi-stages active balun-LNA coupled into a fully balanced passive mixer with an all-pass in-phase/quadrature phase generator. The trans-impedance amplifier converts the input signal current into a voltage gain at the outputs. Simultaneously, the high power input signal current is channelized into an anti-aliasing filter with 20 dB rejection for out of band interferers. In addition, the dissertation demonstrates a wide dynamic range system with small die area, cost effective and very low power consumption

Integrated Circuit and System Design for Cognitive Radio and Ultra-Low Power Applications

The ubiquitous presence of wireless and battery-powered devices is an inseparable and invincible feature of our modern life. Meanwhile, the spectrum aggregation, and limited battery capacity of handheld devices challenge the exploding demand and growth of such radio systems. In this work, we try to present two separate solutions for each case; an ultra-wideband (UWB) receiver for Cognitive Radio (CR) applications to deal with spectrum aggregation, and an ultra-low power (ULP) receiver to enhance battery life of handheld wireless devices. Limited linearity and LO harmonics mixing are two major issues that ultra-wideband receivers, and CR in particular, are dealing with. Direct conversion schemes, based on current-driven passive mixers, have shown to improve the linearity, but unable to resolve LO harmonic mixing problem. They are usually limited to 3rd, and 5th harmonics rejection or require very complex and power hungry circuitry for higher number of harmonics. This work presents a heterodyne up-down conversion scheme in 180 nm CMOS technology for CR applications (54-862 MHz band) that mitigates the harmonic mixing issue for all the harmonics, while by employing an active feedback loop, a comparable to the state-of-the art IIP3 of better than +10 dBm is achieved. Measurements show an average NF of 7.5 dB when the active feedback loop is off (i.e. in the absence of destructive interference), and 15.5 dB when the feedback loop is active and a 0 dBm interferer is applied, respectively. Also, the second part of this work presents an ultra-low power super-regenerative receiver (SRR) suitable for OOK modulation and provides analytical insight into its design procedure. The receiver is fabricated in 40 nm CMOS technology and operates in the ISM band of 902-928 MHz. Binary search algorithm through Successive Approximation Register (SAR) architecture is being exploited to calibrate the internally generated quench signal and the working frequency of the receiver. Employing an on-chip inductor and a single-ended to differential architecture for the input amplifier has made the receiver fully integrable, eliminating the need for external components. A power consumption of 320 µW from a 0.65 V supply results in an excellent energy efficiency of 80 pJ/b at 4 Mb/s data rate. The receiver also employs an ADC that enables soft-decisioning and a convenient sensitivity-data rate trade-off, achieving sensitivity of -86.5, and -101.5 dBm at 1000 and 31.25 kbps data rate, respectivel