Amplificador de Instrumentação de Baixa Potência em Tecnologia CMOS para um Sistema Integrado de Aquisição de Sinal com Sensores MEMS.

Esta dissertação apresenta o estudo de um amplificador de instrumentação integrado de Acomplamento Capacitivo (CCIA) para um analog front-end (AFE), otimizado para extrair sinais de um sensor tipo MEMS de elevada impedância. Este amplificador destina-se à integração num sistema AFE, implementado em tecnologia CMOS de 130 nm, do qual consiste num amplificador de instrumentação, um filtro passa-banda de condensadores comutados, e um conversor analógico digital do tipo sigma − delta. O amplificador de instrumentação é capaz de operar a tensões de alimentação inferiores a 1 V, com uma largura de banda (BW) até 10 kHz Visando a redução do ruido flícker, é utilizado uma técnica de modulação chopper, a qual acarreta uma consequente degradação da impedância de entrada. Todavia, esta é compensada por efeito de uma malha de realimentação positiva. Este amplificador de baixo ruído é constituído por um andar de entrada folded cascode, que recorre a uma técnica de distribuição de corrente para a diminuição de potência dissipada. Para além deste bloco de entrada, o circuito incluí um segundo andar common-drain e um andar de saída common-source. Para uma tensão de alimentação de 1 V, o amplificador de instrumentação apresenta uma potência total consumida de 2.6 µW, uma impedância de entrada superior a 1 GΩ, e um SNR máximo de 107 dB. O ganho em malha aberta é de 87 dB, com um GBW de 583.4 kHz. O ruído referente à entrada obtido é de 4.6 nVrms, com um valor NEF resultante de 4. O CMRR e PSRR obtidos são superiores a 97 dB e 66 dB, respectivamente, com uma área total ocupada de 0.06mm2.This dissertation presents the design of a low-noise capacitively-coupled instrumentation amplifier for an analog front-end (AFE) optimized for the extraction of signals from a high impedance MEMS sensor. This amplifier is part of an AFE which is implemented in a standard 130 nm bulk CMOS technology. Beside the high-impedance input amplifier, the AFE includes a programmable switch-capacitor bandpass filter and a sigma-delta modulator. The instrumentation amplifier is capable to operate with a sub-1 V power supply at a 10 kHz bandwidth. A chopper modulation technique is implemented to further reduce the flicker noise, with a positive feedback network, compensating the resulting low input impedance. The low-noise amplifier consists of a differential input pair folded cascode, using a current splitting technique to decrease the power consumption, with a common-drain configuration and a common source output stage. For a power supply of 1 V, the instrumentation amplifier achieves a total power consumption of 2.6 µW, with an equivalent input impedance greater then 1 GΩ and a maximum SNR of 107 dB. The open loop gain is 87 dB with a GBW of 584 kHz. The measured input referred noise is 4.6 µVrms, with a NEF value of 4. The minimum CMRR of the amplifier is 97 dB and the PSRR minus is 66 dB. The total area occupied is 0.06mm2

Sobre el uso de técnicas chopper para la reducción del ruido flicker en amplificadores para la captación de señales neuronales

La captación de señales neuronales mediante electrodos conectados a circuitos micro-electrónicos es necesaria para aplicaciones clínicas y para el control de prótesis senso-motoras, entre otras muchas aplicaciones bio-médicas. En todas estas aplicaciones, la preservación de la información contenida en las imágenes captadas depende críticamente de las prestaciones de los amplificadores empleados en la cabecera de la cadena de procesamiento electrónica. El problema es que se trata de señales muy débiles (rango de V) y de baja V) y de baja V) y de baja V) y de baja V) y de baja V) y de baja V) y de baja V) y de baja V) y de baja V) y de baja V) y de baja V) y de baja V) y de baja frecuencia (rango de sub-Hz), lo que implica una enorme influencia del ruido flicker. Al margen de esta influencia, el diseño de estos amplificadores, y de las cadenas de procesamiento completas, está condicionado por restricciones severas de área y consumo de potencia. En el Instituto de Microelectrónica de Sevilla está activa una línea de investigación sobre el diseño de interfaces de señal-mixta para captación de señales neuronales. Se han concebido, prototipado en forma de chips y validado mediante medidas “in-vitro” e “in-vivo” chips con 64 canales, con calibración “on-chip” y compresión de la señal “on-chip”, con captación de energía mediante enlaces inductivos. Estos circuitos emplean amplificadores seleccionados mediante técnicas de optimización para conseguir mínimo ruido con mínimo consumo de potencia. Sin embargo, no incluyen técnicas específicas para la reducción del ruido flicker. Además, estudios posteriores han permitido vislumbrar la posibilidad de mejorar las topologías de amplificadores, en particular usando la topología denominada active-feedback time constant enhanced neural amplifier, que se presenta en el Capítulo1 de esta Memoria. Este trabajo Fin de Grado se propone con el objetivo de desarrollar modelos y técnicas para reducción del ruido flicker en amplificadores neuronales, con una doble perspectiva: Modelar dicho ruido en este tipo de amplificadores con vistas a la optimización del diseño de los mismos. Incorporar técnicas de modulación Chopper en los amplificadores neuronales y evaluar su impacto sobre las prestaciones de los amplificadores. En particular, estudiar, a nivel de modelos eléctricos, cómo afecta la aplicación de la técnica de Chopper en amplificadores del tipo active-feedback time constant enhanced neural amplifier. Explorar la posibilidad de generar ruido flicker mediante circuitos simples, adecuados para ser embebidos “on-chip” en sistemas de captación de señales neuronales, con los propósitos, no explorados en este trabajo, de auto-testado y calibración. Los modelos y técnicas propuestas nos han permitido reducir hasta 40dB la potencia del ruido en el amplificador para frecuencias inferiores a 1 Hz, lo cual nos permite constatar la validez de los resultados. De hecho, sobre la base de estos resultados, se está trabajando en la actualidad para diseñar y prototipar un chip que integra las soluciones propuestas en este trabajo. Respecto a la generación de ruido “on-chip” se han propuesto combinaciones de mapas discretos que pueden ser parametrizados para obtener densidades espectrales de potencia con distribución frecuencia propia de distintos tipos de ruido pertinentes para los objetivos del trabajo.The uptake of neural signals through electrodes attached to micro-electronic circuits is needed for clinical applications and control sensorimotor prostheses, among many other bio-medical applications. In all these applications, the preservation of the information contained in the captured images depends critically on the performance of the amplifiers used in the header of the electronic processing chain. The problem is that there are very weak (V range) and low frequency (sub - Hz range) signals, which implies a huge influence of flicker noise. Apart from this influence, the design of these amplifiers, and complete processing chain, is conditioned by severe restrictions of area and power consumption. At the Institute of Microelectronics of Seville there is an active research on the interface design- mixed signal to seize neural signals. They are designed, prototyping in the form of chips and validated using measures "in-vitro" and "in-vivo" chips with 64 channels, calibrated on-chip and signal compression on-chip with capture energy by inductive links. These circuits employ amplifiers selected by optimization techniques to achieve minimal noise with minimal power consumption. However, they do not include specific techniques to reduce the flicker noise. In addition, further studies have allowed to glimpse the possibility of improving this kind of amplifiers, particularly using the topology called active-feedback time constant neural enhanced amplifier, which is presented in Chapter 1 of this Report. This work is proposed with the aim of developing models and techniques for reducing flicker noise in neural amplifiers with a dual perspective: Modeling such noise in this type of amplifiers with the purpose of optimizing their design. Incorporate Chopper modulation techniques in neural amplifiers and assess their impact on the performance of amplifiers. In particular, to study at electric models level, how the application of the technique Chopper affects amplifiers of the active-feedback amplifier time constant neural enhanced kind. Explore the possibility to generate flicker noise by simple circuits, suitables for embedded on-chip systems for capturing neural signals, for purposes not explored in this work, as self-testing and calibration. The proposed models and techniques have allowed us to reduce up to 40dB noise power in the amplifier for less than 1 Hz frequencies, which let us verify the validity of the results. In fact, there is currently some work based on these results to design and prototype a chip that integrates the solutions proposed in this project. Regarding noise generation on-chip, it has been proposed combinations of discrete maps that can be parameterized to obtain spectral power densities with natural frequency distribution of different types of noise, relevant to the objectives of the work.Universidad de Sevilla. Grado en Ingeniería Electrónica, Robótica y Mecatrónic

Ultra-low power mixed-signal frontend for wearable EEGs

Electronics circuits are ubiquitous in daily life, aided by advancements in the chip design industry, leading to miniaturised solutions for typical day to day problems. One of the critical healthcare areas helped by this advancement in technology is electroencephalography (EEG). EEG is a non-invasive method of tracking a person's brain waves, and a crucial tool in several healthcare contexts, including epilepsy and sleep disorders. Current ambulatory EEG systems still suffer from limitations that affect their usability. Furthermore, many patients admitted to emergency departments (ED) for a neurological disorder like altered mental status or seizures, would remain undiagnosed hours to days after admission, which leads to an elevated rate of death compared to other conditions. Conducting a thorough EEG monitoring in early-stage could prevent further damage to the brain and avoid high mortality. But lack of portability and ease of access results in a long wait time for the prescribed patients. All real signals are analogue in nature, including brainwaves sensed by EEG systems. For converting the EEG signal into digital for further processing, a truly wearable EEG has to have an analogue mixed-signal front-end (AFE). This research aims to define the specifications for building a custom AFE for the EEG recording and use that to review the suitability of the architectures available in the literature. Another critical task is to provide new architectures that can meet the developed specifications for EEG monitoring and can be used in epilepsy diagnosis, sleep monitoring, drowsiness detection and depression study. The thesis starts with a preview on EEG technology and available methods of brainwaves recording. It further expands to design requirements for the AFE, with a discussion about critical issues that need resolving. Three new continuous-time capacitive feedback chopped amplifier designs are proposed. A novel calibration loop for setting the accurate value for a pseudo-resistor, which is a crucial block in the proposed topology, is also discussed. This pseudoresistor calibration loop achieved the resistor variation of under 8.25%. The thesis also presents a new design of a curvature corrected bandgap, as well as a novel DDA based fourth-order Sallen-Key filter. A modified sensor frontend architecture is then proposed, along with a detailed analysis of its implementation. Measurement results of the AFE are finally presented. The AFE consumed a total power of 3.2A (including ADC, amplifier, filter, and current generation circuitry) with the overall integrated input-referred noise of 0.87V-rms in the frequency band of 0.5-50Hz. Measurement results confirmed that only the proposed AFE achieved all defined specifications for the wearable EEG system with the smallest power consumption than state-of-art architectures that meet few but not all specifications. The AFE also achieved a CMRR of 131.62dB, which is higher than any studied architectures.Open Acces

Design of agile signal conditioning circuits for microelectromechanical sensors

Microelectromechanical systems (MEMS) are used in many applications to detect physical parameters and convert them to an electrical signal. The output of MEMS-based transducers is usually not suitable to be directly processed in the digital or the analog domain, and they could be as small as femto farads in capacitive sensing and micro volts in resistive sensing. Consequently, high sensitivity signal conditioning circuits are essential. In this thesis, it is shown that both the noise and input capacitance are important parameters to ensure optimal capacitive sensing. The dominant noise source in MEMS conditioning circuits is flicker noise, and one of the best methods to mitigate flicker noise is the chopping technique. Three different chopping techniques are considered: single chopper amplifier (SCA), dual chopper amplifier (DCA), and two-stage single chopper amplifier (TCA). Also, their sensitivity and power consumption based on the total gain and sensing capacitance are extracted. It is shown that the distribution of gain between the two stages in the DCA and TCA has a significant effect on the sensitivity, and, based on this distribution, the sensitivity and power consumption change significantly. For small sensor capacitances, the highest sensitivity could be achieved by a DCA because of its ability to decrease the noise floor and the input sensor capacitance simultaneously. A novel DCA is proposed to reach higher sensitivity and reduced power consumption. In this DCA, two supply voltages are utilized, and the second stage is composed of two parallel paths that improve the SNR and provide two gain settings. This circuit is fabricated in the GlobalFoundries 0.13 μm CMOS technology. The measurement results show a power consumption of 2.66 μW for the supply voltage of 0.7 V and of 3.26 μW for the supply voltage of 1.2 V. The single path DCA has a gain of 34 dB with bandwidth of 4 kHz and input noise floor of 25 nV/√Hz. The dual path DCA has a gain of 38 dB with bandwidth of 3 kHz and input noise floor of 40 nV/√Hz. To be able to detect the signal near DC frequencies, another circuit is proposed which has a configurable bandwidth and a sub-μHz noise corner frequency. This circuit is composed of three stages, and three chopping frequencies are used to mitigate the flicker noise of the three stages. The simulated circuit is designed in the GlobalFoundries 0.13 μm CMOS technology with supply voltages of 0.4 V and 1.2 V. The total power consumption is of 6.7 μW. A gain of 68 dB and bandwidths of 1, 10, 100 and 1000 Hz are achieved. The input referred noise floor is of 20.5 nV/√Hz and the design attains a good power efficiency factor of 4.0. In the capacitive mode, the noise floor is of 3.6 zF for a 100 fF capacitance sensor