Quadrature Phase-Domain ADPLL with Integrated On-line Amplitude Locked Loop Calibration for 5G Multi-band Applications

5th generation wireless systems (5G) have expanded frequency band coverage with the low-band 5G and mid-band 5G frequencies spanning 600 MHz to 4 GHz spectrum. This dissertation focuses on a microelectronic implementation of CMOS 65 nm design of an All-Digital Phase Lock Loop (ADPLL), which is a critical component for advanced 5G wireless transceivers. The ADPLL is designed to operate in the frequency bands of 600MHz-930MHz, 2.4GHz-2.8GHz and 3.4GHz-4.2GHz. Unique ADPLL sub-components include: 1) Digital Phase Frequency Detector, 2) Digital Loop Filter, 3) Channel Bank Select Circuit, and 4) Digital Control Oscillator. Integrated with the ADPLL is a 90-degree active RC-CR phase shifter with on-line amplitude locked loop (ALL) calibration to facilitate enhanced image rejection while mitigating the effects of fabrication process variations and component mismatch. A unique high-sensitivity high-speed dynamic voltage comparator is included as a key component of the active phase shifter/ALL calibration subsystem. 65nm CMOS technology circuit designs are included for the ADPLL and active phase shifter with simulation performance assessments. Phase noise results for 1 MHz offset with carrier frequencies of 600MHz, 2.4GHz, and 3.8GHz are -130, -122, and -116 dBc/Hz, respectively. Monte Carlo simulations to account for process variations/component mismatch show that the active phase shifter with ALL calibration maintains accurate quadrature phase outputs when operating within the frequency bands 600MHz-930MHz, 2.4GHz-2.8GHz and 3.4GHz-4.2GHz

RF CMOS receiver front-end using a reflex amplifier

A concept for an RF-CMOS receiver with reflex topology is developed and tested, using OrCad as the primary design and simulation tool. The main idea of the reflex topology is to reuse a Low Noise Amplifier (LNA) stage in the circuit and thus eliminate one high power consumption stage. A Gilbert cell is used for down conversion, with the benefit of low noise and low power while maintaining gain. A set of passive diplexers allows reuse of the LNA at the RF and IF. The complete circuit was simulated using 0.18 micron and 0.5 micron AMI technology. Parameters for the transistors are imported from MOSIS development tools and design specifications for the purpose of production of this device. The overall system was simulated using the 900 MHz frequency for radio frequency (RF) and shows substantial gain and low noise figure. Lastly, the Gilbert cell mixer has been modified in an attempt to further reduce power consumption. Instead of using a local oscillator, we designed the Gilbert cell so it would self-oscillate. Output results and linearity characteristics are shown through simulation

A Q-band Direct Divide-by-4 Injection-Locked Frequency Divider with Quadrature Outputs

[[abstract]]A divide-by-4 injection-locked frequency divider is designed for applications in the millimeter-wave frequency range. The proposed circuit also features in quadrature phase outputs by using a quadrature voltage-controlled oscillator. The input signal is injected into the common-mode node at the tail current source directly. Implemented in a 0.13 μm CMOS technology, the core circuit consumes dc power of 3.66mW with 1.2 V supply voltage. The operation range achieves 1.95 GHz. The entire die occupies an area of 974Ã726 um 2 .[[conferencetype]]國際[[conferencedate]]20100928~2010093

System-on-Package Low-Power Telemetry and Signal Conditioning unit for Biomedical Applications

Recent advancements in healthcare monitoring equipments and wireless communication technologies have led to the integration of specialized medical technology with the pervasive wireless networks. Intensive research has been focused on the development of medical wireless networks (MWN) for telemedicine and smart home care services. Wireless technology also shows potential promises in surgical applications. Unlike conventional surgery, an expert surgeon can perform the surgery from a remote location using robot manipulators and monitor the status of the real surgery through wireless communication link. To provide this service each surgical tool must be facilitated with smart electronics to accrue data and transmit the data successfully to the monitoring unit through wireless network. To avoid unwieldy wires between the smart surgical tool and monitoring units and to reap the benefit of excellent features of wireless technology, each smart surgical tool must incorporate a low-power wireless transmitter. Low-power transmitter with high efficiency is essential for short range wireless communication. Unlike conventional transmitters used for cellular communication, injection-locked transmitter shows greater promises in short range wireless communication. The core block of an injection-locked transmitter is an injection-locked oscillator. Therefore, this research work is directed towards the development of a low-voltage low-power injection-locked oscillator which will facilitate the development of a low-power injection-locked transmitter for MWN applications. Structure of oscillator and types of injection are two crucial design criteria for low-power injection-locked oscillator design. Compared to other injection structures, body-level injection offers low-voltage and low-power operation. Again, conventional NMOS/PMOS-only cross-coupled LC oscillator can work with low supply voltage but the power consumption is relatively high. To overcome this problem, a self-cascode LC oscillator structure has been used which provides both low-voltage and low-power operation. Body terminal coupling is used with this structure to achieve injection-locking. Simulation results show that the self-cascode structure consumes much less power compared to that of the conventional structure for the same output swing while exhibiting better phase noise performance. Usage of PMOS devices and body bias control not only reduces the flicker noise and power consumption but also eliminates the requirements of expensive fabrication process for body terminal access

RF CMOS quadrature voltage-controlled oscillator design using superharmonic coupling method.

Chung, Wai Fung.Thesis (M.Phil.)--Chinese University of Hong Kong, 2007.Includes bibliographical references (leaves 98-100).Abstracts in English and Chinese.摘要 --- p.IIIACKNOWLEDGEMENT --- p.IVCONTENTS --- p.VLIST OF FIGURES --- p.VIIILIST OF TABLES --- p.XLIST OF TABLES --- p.XChapter CHAPTER 1 --- INTRODUCTION --- p.1Chapter 1.1 --- Motivation --- p.1Chapter 1.2 --- Receiver Architecture --- p.3Chapter 1.2.1 --- Zero-IF Receivers --- p.4Chapter 1.2.2 --- Low-IF Receivers --- p.6Chapter 1.2.2.1 --- Hartley Architecture --- p.7Chapter 1.2.2.2 --- Weaver Architecture --- p.9Chapter 1.3 --- Image-rejection ratio --- p.10Chapter 1.4 --- Thesis Organization --- p.12Chapter CHAPTER 2 --- FUNDAMENTALS OF OSCILLATOR --- p.13Chapter 2.1 --- Basic Oscillator Theory --- p.13Chapter 2.2 --- Varactor --- p.15Chapter 2.3 --- Inductor --- p.17Chapter 2.4 --- Phase noise --- p.22Chapter 2.4.1 --- The Leeson ´ةs phase noise expression --- p.24Chapter 2.4.2 --- Linear model --- p.25Chapter 2.4.3 --- Linear Time-Variant phase noise model --- p.28Chapter CHAPTER 3 --- FULLY-INTEGRATED CMOS OSCILLATOR DESIGN --- p.31Chapter 3.1 --- Ring oscillator --- p.31Chapter 3.2 --- LC oscillator --- p.33Chapter 3.2.1 --- LC-tank resonator --- p.34Chapter 3.2.2 --- Negative transconductance --- p.36Chapter 3.3 --- Generation of quadrature phase signals --- p.39Chapter 3.4 --- Quadrature VCO topologies --- p.41Chapter 3.4.1 --- Parallel-coupled QVCO --- p.41Chapter 3.4.2 --- Series-coupled QVCO --- p.46Chapter 3.4.3 --- QVCO with Back-gate Coupling --- p.47Chapter 3.4.4 --- QVCO using superharmonic coupling --- p.49Chapter 3.5 --- Novel QVCO using back-gate superharmonic coupling --- p.52Chapter 3.5.1 --- Tuning range --- p.54Chapter 3.5.2 --- Negative gm --- p.55Chapter 3.5.3 --- Phase noise calculation --- p.56Chapter 3.5.4 --- Coupling coefficient --- p.57Chapter 3.5.5 --- Low-voltage and low-power design --- p.59Chapter 3.5.6 --- Layout Consideration --- p.61Chapter 3.5.6.1 --- Symmetrical Layout and parasitics --- p.61Chapter 3.5.6.2 --- Metal width and number of vias --- p.63Chapter 3.5.6.3 --- Substrate contact and guard ring --- p.63Chapter 3.5.7 --- Simulation Results --- p.65Chapter 3.5.7.1 --- Frequency and output power --- p.65Chapter 3.5.7.2 --- Quadrature signal generation --- p.67Chapter 3.5.7.3 --- Tuning range --- p.67Chapter 3.5.7.4 --- Power consumption --- p.68Chapter 3.5.7.5 --- Phase noise --- p.69Chapter 3.6 --- Polyphase filter and Single-sideband mixer design --- p.70Chapter 3.6.1 --- Polyphase filter --- p.72Chapter 3.6.2 --- Layout Consideration --- p.74Chapter 3.6.3 --- Simulation results --- p.76Chapter 3.7 --- Comparison with parallel-coupled QVCO --- p.78Chapter CHAPTER 4 --- EXPERIMENTAL RESULTS --- p.80Chapter 4.1 --- Test Fixture --- p.82Chapter 4.2 --- Measurement set-up --- p.84Chapter 4.3 --- Measurement results --- p.86Chapter 4.3.1 --- Proposed QVCO using back-gate superharmonic coupling --- p.86Chapter 4.3.1.1 --- Output Spectrum --- p.86Chapter 4.3.1.2 --- Tuning range --- p.87Chapter 4.3.1.3 --- Phase noise --- p.88Chapter 4.3.1.4 --- Power consumption --- p.88Chapter 4.3.1.5 --- Image-rejection ratio --- p.89Chapter 4.3.2 --- Parallel-coupled QVCO --- p.90Chapter 4.3.2.1 --- Output spectrum --- p.90Chapter 4.3.2.2 --- Power consumption --- p.90Chapter 4.3.2.3 --- Tuning range --- p.91Chapter 4.3.2.4 --- Phase noise --- p.92Chapter 4.3.3 --- Comparison between proposed and parallel-coupled QVCO --- p.93Chapter CHAPTER 5 --- CONCLUSIONS --- p.95Chapter 5.1 --- Conclusions --- p.95Chapter 5.2 --- Future work --- p.97REFERENCES --- p.9

A Fully-Integrated Reconfigurable Dual-Band Transceiver for Short Range Wireless Communications in 180 nm CMOS

© 2015 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other users, including reprinting/ republishing this material for advertising or promotional purposes, creating new collective works for resale or redistribution to servers or lists, or reuse of any copyrighted components of this work in other works.A fully-integrated reconfigurable dual-band (760-960 MHz and 2.4-2.5 GHz) transceiver (TRX) for short range wireless communications is presented. The TRX consists of two individually-optimized RF front-ends for each band and one shared power-scalable analog baseband. The sub-GHz receiver has achieved the maximum 75 dBc 3rd-order harmonic rejection ratio (HRR3) by inserting a Q-enhanced notch filtering RF amplifier (RFA). In 2.4 GHz band, a single-ended-to-differential RFA with gain/phase imbalance compensation is proposed in the receiver. A ΣΔ fractional-N PLL frequency synthesizer with two switchable Class-C VCOs is employed to provide the LOs. Moreover, the integrated multi-mode PAs achieve the output P1dB (OP1dB) of 16.3 dBm and 14.1 dBm with both 25% PAE for sub-GHz and 2.4 GHz bands, respectively. A power-control loop is proposed to detect the input signal PAPR in real-time and flexibly reconfigure the PA's operation modes to enhance the back-off efficiency. With this proposed technique, the PAE of the sub-GHz PA is improved by x3.24 and x1.41 at 9 dB and 3 dB back-off powers, respectively, and the PAE of the 2.4 GHz PA is improved by x2.17 at 6 dB back-off power. The presented transceiver has achieved comparable or even better performance in terms of noise figure, HRR, OP1dB and power efficiency compared with the state-of-the-art.Peer reviewe

Design And Implementation Of Up-Conversion Mixer And Lc-Quadrature Oscillator For IEEE 802.11a WLAN Transmitter Application Utilizing 0.18 Pm CMOS Technology [TK7871.99.M44 H279 2008 f rb].

Perlumbaan implementasi litar terkamil radio, dengan kos yang rendah telah menggalakkan penggunaan teknologi CMOS. The drive for cost reduction has led to the use of CMOS technology for highly integrated radios

A 12GHz 30mW 130nm CMOS Rotary Travelling Wave Voltage Controlled Oscillator

This paper reports a 12GHz Rotary Travelling Wave (RTW) Voltage Controlled Oscillator designed in a 130nm CMOS technology. The phase noise and power consumption performances were compared with the literature and with telecommunication standards for broadcast satellite applications. The RTW VCO exhibits a -106dBc/Hz@1MHz and a 30mW power consumption with a sensibility of 400 MHz/V. Finally, requirements are given for a PLL implementation of the RTW VCO and simulated results are presented