3 research outputs found
A 9.38-bit, 422nW, high linear SAR-ADC for wireless implantable system
In wireless implantable systems (WIS) low power consumption and linearity are the most prominent performance metrics in data acquisition systems. successive approximation register-analog to digital converter (SAR-ADC) is used for data processing in WIS. In this research work, a 10-bit low power high linear SAR-ADC has been designed for WIS. The proposed SAR-ADC architecture is designed using the sample and hold (S/H) circuit consisting of a bootstrap circuit with a dummy switch. This SAR-ADC has a dynamic latch comparator, a split capacitance digital to analog converter (SC-DAC) with mismatch calibration, and a SAR using D-flipflop. This architecture is designed in 45 nm CMOS technology. This ADC reduces non-linearity errors and improve the output voltage swing due to the usage of a clock booster and dummy switch in the sample and hold. The calculated outcomes of the proposed SAR ADC display that with on-chip calibration an ENOB of 9.38 (bits), spurious free distortion ratio (SFDR) of 58.621 dB, and ± 0.2 LSB DNL and ± 0.4LSB INL after calibration
Design of Analog-to-Digital Converters with Embedded Mixing for Ultra-Low-Power Radio Receivers
In the field of radio receivers, down-conversion methods usually rely on one (or more)
explicit mixing stage(s) before the analog-to-digital converter (ADC). These stages not
only contribute to the overall power consumption but also have an impact on area and can
compromise the receiver’s performance in terms of noise and linearity. On the other hand,
most ADCs require some sort of reference signal in order to properly digitize an analog
input signal. The implementation of this reference signal usually relies on bandgap
circuits and reference buffers to generate a constant, stable, dc signal. Disregarding this
conventional approach, the work developed in this thesis aims to explore the viability
behind the usage of a variable reference signal. Moreover, it demonstrates that not only
can an input signal be properly digitized, but also shifted up and down in frequency,
effectively embedding the mixing operation in an ADC. As a result, ADCs in receiver
chains can perform double-duty as both a quantizer and a mixing stage. The lesser known
charge-sharing (CS) topology, within the successive approximation register (SAR) ADCs,
is used for a practical implementation, due to its feature of “pre-charging” the reference
signal prior to the conversion. Simulation results from an 8-bit CS-SAR ADC designed in
a 0.13 ÎĽm CMOS technology validate the proposed technique