Simulation of Non-linear Applications of Operation Amplifiers in Orcad System

Náplní bakalářské práce je řešení nelineárních aplikací operačních zesilovačů. V práci bude obsažen teoretický úvod se zaměřením na problematiku operačních zesilovačů, následný rozbor některých jeho funkcí, činnosti a možnou modulaci jeho signálů. Práce obsahuje návrhy jako je invertující a neinvertující komparátor s hysterezní obvodem, jeho následná parametrizace součástek, analýza průběhu v stejnosměrné a časové oblasti.The scope of the bachelor thesis is the solution of nonlinear applications of operational amplifiers. The thesis contains a theoretical introduction focusing on the problems of operational amplifiers, followed by an analysis of some of its functions, operation and possible modulation of its signals. The thesis includes designs such as inverting and non-inverting comparator with hysteresis circuit, its subsequent component parameterization, waveform analysis in DC and time domain.430 - Katedra elektronikydobř

Accelerated Successive Approximation Technique for Analog to Digital Converter Design

This thesis work presents a novel technique to reduce the number of conversion cycles for Successive Approximation register (SAR) Analog to Digital Converters (ADC), thereby potentially improving the conversion speed as well as reducing its power consumption. Conventional SAR ADCs employ the binary search algorithm and they update only one bound, either the upper or lower bound, of the search space during one conversion cycle. The proposed method, referred to as the Accelerated-SAR or A-SAR, is capable of updating both the lower and upper bounds in a single conversion cycle. Even in cases that it can update only one bound, it does more aggressively. The proposed technique is implemented in a 10-bit SAR ADC circuit with 0.5V power supply and rail-to-rail input range. To cope with the ultra-low voltage design challenge, Time-to-Digital conversion techniques are used in the implementation. Important design issues are also discussed for the charge scaling array and Voltage Controlled Delay Lines (VCDL), which are important building blocks in the ADC implementation

Ultra-low Power Circuits for Internet of Things (IOT)

Miniaturized sensor nodes offer an unprecedented opportunity for the semiconductor industry which led to a rapid development of the application space: the Internet of Things (IoT). IoT is a global infrastructure that interconnects physical and virtual things which have the potential to dramatically improve people's daily lives. One of key aspect that makes IoT special is that the internet is expanding into places that has been ever reachable as device form factor continue to decreases. Extremely small sensors can be placed on plants, animals, humans, and geologic features, and connected to the Internet. Several challenges, however, exist that could possibly slow the development of IoT. In this thesis, several circuit techniques as well as system level optimizations to meet the challenging power/energy requirement for the IoT design space are described. First, a fully-integrated temperature sensor for battery-operated, ultra-low power microsystems is presented. Sensor operation is based on temperature independent/dependent current sources that are used with oscillators and counters to generate a digital temperature code. Second, an ultra-low power oscillator designed for wake-up timers in compact wireless sensors is presented. The proposed topology separates the continuous comparator from the oscillation path and activates it only for short period when it is required. As a result, both low power tracking and generation of precise wake-up signal is made possible. Third, an 8-bit sub-ranging SAR ADC for biomedical applications is discussed that takes an advantage of signal characteristics. ADC uses a moving window and stores the previous MSBs voltage value on a series capacitor to achieve energy saving compared to a conventional approach while maintaining its accuracy. Finally, an ultra-low power acoustic sensing and object recognition microsystem that uses frequency domain feature extraction and classification is presented. By introducing ultra-low 8-bit SAR-ADC with 50fF input capacitance, power consumption of the frontend amplifier has been reduced to single digit nW-level. Also, serialized discrete Fourier transform (DFT) feature extraction is proposed in a digital back-end, replacing a high-power/area-consuming conventional FFT.PHDElectrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttps://deepblue.lib.umich.edu/bitstream/2027.42/137157/1/seojeong_1.pd

심전도 감시 분야를 위한 저전력 신호 특화된 축차 비교형 아날로그-디지털 변환기의 설계

학위논문 (박사)-- 서울대학교 대학원 공과대학 전기·컴퓨터공학부, 2017. 8. 김수환.Electrocardiography is an indispensable tool employed for diagnosis of cardiovascular diseases. When electrocardiograms (ECGs) need to be monitored for a long time, e.g. to diagnose arrhythmia, a device has to be worn or implanted under the skin, which requires low energy consumption. Successive approximation register analog-to-digital converters (SAR ADCs) have been especially preferred in low power applications, while the recent trend of ADC designs shows that the SAR ADCs find a much wide range of applications, and are the most versatile ADC architecture. The subject of the dissertation is the design of a signal-specific SAR ADC scheme that reduces the power consumption by exploiting the characteristics of the input signal of a particular type whose signal activity is low on average and dichotomous, as best exemplified by ECGs. This dissertation presents a 1.8-V 10-bit 1-kS/s low-power SAR ADC with the proposed signal-specific switching algorithm. The proposed adaptive switching algorithm has two operation modes suitable for the dichotomous activity of the ECG: full switching mode that resolves the full range of the input as an ordinary SAR ADC, and reduced switching mode that assumes 5 MSBs will not change and samples just the rest LSB portion and resolves it in 5 bitcycles. The reduced number of bitcycles yields saving in switching power consumption. For smooth mode change adaptive to the input signal activity, an additional function in each mode, viz., MSBs tracking in full switching mode and LSBs extrapolation in reduced switching mode, runs concurrently with the respective main operation. A behavioral model of the proposed SAR ADC with the segmented capacitor digital-to-analog converter (CDAC) topology was created in MATLAB and was used in the tests, which verified the function and effectiveness of the adaptive switching algorithm. The model describes the evolution of all internal node voltages in the CDAC by each switching action, from which the charge variation in each capacitor and the switching energy consumption can be computed. The model was extensively used for the development and analysis of the idea. The 5-bit size of the MSB section was determined from the simulation results with the behavioral model. A prototype chip was fabricated in 0.18-μm CMOS technology. Measurements with an ECG type input proved the suitability of the adaptive switching for ECG monitoring. The power reduction by the adaptive switching in each of comparator, logic, and DAC power domains was calculated from the measurements of both cases of the adaptive-switching and fixed-full-switching operations, the latter of which is equivalent to the conventional SAR ADC operation. It achieved a reduction in comparator power consumption by 39%. The DAC power, i.e. the switching power consumed in the CDAC, achieved a reduction by 1.28 nW, which is close to the result of the behavioral model simulation. The reduction in the logic power domain was 12%. In terms of total power consumption, the adaptive switching consumed 91.02 nW while the fixed full switching consumed 107.51 nW. The reduction corresponds to 15.3% in proportion. In addition, the intrinsic performance of the ADC was measured using a sinusoidal input. It achieved a signal-to-noise-and-distortion ratio of 56.24 dB and a spurious-free dynamic range of 62.00 dB. The maximum differential nonlinearity of +0.39/−1 LSBs and maximum integral nonlinearity of +0.86/−1.5 LSBs were measured. The main source of the nonlinearity is the capacitor mismatch in the CDAC.심전도는 심혈관계 질환의 진단을 위한 중요한 자료로서 감시 및 기록된다. 때로 부정맥 진단 등을 위하여 심전도를 오랜 시간 관찰해야 할 경우, 착용 가능한(웨어러블) 장비나 체내에 이식할 수 있는 장비를 사용해야 하는데, 이들은 전력 소비가 적어야 한다. 축차 비교형 아날로그-디지털 변환기(SAR ADC)는 저전력 응용 분야에서 주로 선호한 구조였으나 최근 아날로그-디지털 변환기 설계의 추세는 SAR ADC가 훨씬 넓은 응용 분야에 적용 가능하며 가장 넓은 범용성을 가진 구조임을 보여준다. 본 논문의 주제는 심전도 신호처럼 양분된 신호 활성도를 가지면서 평균 신호 활성도는 낮은 유형의 신호를 대상으로, 이 특성을 이용하여 전력의 소비를 낮추는 신호 특화된 스위칭 기법을 적용한 SAR ADC 설계이다. 본 논문에서는 신호 특화된 기법을 적용한 1.8V, 10 bit, 1kS/s의 저전력 SAR ADC 설계를 제시한다. 제안하는 적응형 스위칭 기법은 ECG의 양분된 신호 활성도 특성에 맞추어, 일반적인 SAR ADC처럼 입력의 전체 범위를 처리하는 full switching mode와, 5-bit MSB code가 변하지 않을 것이라는 가정하에 나머지 LSB 부분만 샘플링하고 처리하는 reduced switching mode의 두 가지 동작 모드를 가진다. 입력 신호 활성도에 따라 유연하게 동작 모드를 전환하기 위하여, full switching mode는 MSBs tracking, reduced switching mode는 LSBs extrapolation라는 부가 기능이 각 모드의 주 기능과 함께 동작한다. 제안한 SAR ADC의 behavioral model을 MATLAB에서 만들었고, 이를 이용한 여러 테스트에서 적응형 스위칭 기법의 기능과 효과를 검증하였다. 이 behavioral model은 SAR ADC 내에 있는 segmented CDAC의 모든 내부 node 전압의 변화를 개별 스위칭 동작에 대해 기술하므로, 이를 이용하여 각 캐패시터에 저장된 전하의 변화량이나 스위칭 에너지 소비량을 계산할 수 있다. 이 model을 idea 개발 및 분석에 광범위하게 이용하였다. 0.18μm CMOS 공정에서 시제품 칩을 제작하였다. 심전도 유형의 입력 신호를 이용한 측정을 통해 제안한 적응형 스위칭 기법이 심전도 감시 분야에 적합함을 증명하였다. 제안한 기법으로 얻어지는 ADC의 전력 감소는 제안한 적응형 스위칭으로 동작한 경우와 full switching mode로 고정된 경우(기존의 SAR ADC 동작에 해당)에서 비교기, 논리 회로, DAC 3개 영역의 전력 측정값에서 계산하였다. 비교기 회로의 전력 소비는 39% 줄었다. DAC에서 소비된 전력, 즉 CDAC의 switching 전력 소비량은 1.28 nW가 감소했는데, behavioral model의 simulation 결과와 비슷한 값이다. 논리 회로 영역에서는 12%가 줄었다. 전체 전력 소비는 적응형 스위칭 기법을 적용했을 때 91.02 nW, full switching mode로 고정했을 때 107.51 nW으로 15.3% 감소하였다. 또, sine 입력을 이용하여 설계한 ADC의 기본 성능을 측정하였다. 그 결과 56.24dB의 SNDR과 62.00 dB의 SFDR을 얻었고, 비선형성 지표인 최대 DNL과 INL은 각각 +0.39/−1 LSBs와 +0.86/−1.5 LSBs 을 얻었다. 이 비선형성 특성은 주로 CDAC 내의 캐패시터 미스매치에 기인한 것이다.Chapter 1 Introduction 1 1.1 Electrocardiography 1 1.2 Recent Trends in SAR ADC Designs 4 1.3 Dissertation Contributions and Organization 7 Chapter 2 SAR ADC Operation and Design Issues 9 2.1 Operation Principle 9 2.2 Switching Algorithms for Power Reduction 12 2.2.1 Computation of Switching Energy Consumption 12 2.2.2 Conventional Charge-Redistribution Switching 15 2.2.3 Split-Capacitor Switching 16 2.2.4 Energy-Saving Switching 18 2.2.5 Set-and-Down Switching 21 2.2.6 Merged-Capacitor Switching 22 2.3 Offset and Noise 25 2.4 Linearity 29 2.5 Area 32 Chapter 3 Adaptive Switching SAR ADC for ECG Monitoring Applications 34 3.1 ECG Characteristics and Readout Circuit 34 3.1.1 ECG Signals and Characteristics 34 3.1.2 ECG Readout Circuit 35 3.2 Related Signal-Specific Works 37 3.2.1 SAR ADC with a Bypass Window for Neural Signals 37 3.2.2 LSB-First Successive Approximation 39 3.3 Adaptive Switching 41 3.3.1 Motivation 41 3.3.2 Preliminary Test 42 3.3.3 Algorithm 46 3.3.4 Energy Consumption of SAR ADC with Segmented CDAC 54 3.3.5 Behavioral Model Simulations 59 3.3.6 Consideration on Other Applications 75 3.4 Circuit Implementation 76 3.4.1 Overview 76 3.4.2 Comparator and CDAC 78 3.4.3 Adaptive Switching Logic 81 Chapter 4 Prototype Measurements 86 4.1 Fabrication and Experiment Setup 86 4.2 Measurements 88 4.2.1 Power Reduction Measurement with ECG-Type Input 88 4.2.2 Intrinsic Performance Measurement with Sinusoidal Input 93 4.2.3 Summary of the Measurements and Specifications 96 Chapter 5 Conclusion 98 Bibliography 101 Abstract in Korean 107Docto

Analog and Mixed Signal Design towards a Miniaturized Sleep Apnea Monitoring Device

Sleep apnea is a sleep-induced breathing disorder with symptoms of momentary and often repetitive cessations in breathing rhythm or sustained reductions in breathing amplitude. The phenomenon is known to occur with varying degrees of severity in literally millions of people around the world and cause a range of chronicle health issues. In spite of its high prevalence and serious consequences, nearly 80% of people with sleep apnea condition remain undiagnosed. The current standard diagnosis technique, termed polysomnography or PSG, requires the patient to schedule and undergo a complex full-night sleep study in a specially-equipped sleep lab. Due to both high cost and substantial inconvenience, millions of apnea patients are still undiagnosed and thus untreated. This research work aims at a simple, reliable, and miniaturized solution for in-home sleep apnea diagnosis purposes. The proposed solution bears high-level integration and minimal interference with sleeping patients, allowing them to monitor their apnea conditions at the comfort of their homes. Based on a MEMS sensor and an effective apnea detection algorithm, a low-cost single-channel apnea screening solution is proposed. A custom designed IC chip implements the apnea detection algorithm using time-domain signal processing techniques. The chip performs autonomous apnea detection and scoring based on the patient’s airflow signals detected by the MEMS sensor. Variable sensitivity is enabled to accommodate different breathing signal amplitudes. The IC chip was fabricated in standard 0.5-μm CMOS technology. A prototype device was designed and assembled including a MEMS sensor, the apnea detection IC chip, a PSoC platform, and wireless transceiver for data transmission. The prototype device demonstrates a valuable screening solution with great potential to reach the broader public with undiagnosed apnea conditions. In a battery-operated miniaturized medical device, an energy-efficient analog-to-digital converter is an integral part linking the analog world of biomedical signals and the digital domain with powerful signal processing capabilities. This dissertation includes the detailed design of a successive approximation register (SAR) ADC for ultra-low power applications. The ADC adopts an asynchronous 2b/step scheme that halves both conversion time and DAC/digital circuit’s switching activities to reduce static and dynamic energy consumption. A low-power sleep mode is engaged at the end of all conversion steps during each clock period. The technical contributions of this ADC design include an innovative 2b/step reference scheme based on a hybrid R-2R/C-3C DAC, an interpolation-assisted time-domain 2b comparison scheme, and a TDC with dual-edge-comparison mechanism. The prototype ADC was fabricated in 0.18μm CMOS process with an active area of 0.103 mm^(2), and achieves an ENoB of 9.2 bits and an FoM of 6.7 fJ/conversion-step at 100-kS/s

Conception d'un réseau de plots configurables multifonctions analogiques et numériques combiné à un réseau de distribution de puissance intégrés à l'échelle de la tranche de silicium

RÉSUMÉ De nos jours, les systèmes électroniques sont en constante croissance en taille et en complexité. Cette complexité combinée à la réduction du temps de mise en marché rendant le design de systèmes électroniques un grand défi pour les designers. Une plateforme de prototypage a récemment été introduite afin de s’attaquer toutes ces contraintes à la fois. Cette plateforme s’appuie sur l’implémentation d’un circuit configurable à l’échelle d’une tranche de silicium complète de 200mm de diamètre. Cette surface est recouverte d’une mer de plots conducteurs configurables appelés NanoPads. Ces NanoPads sont suffisamment petits pour supporter des billes d’un diamètre de 250 μm et d’un espacement de 500 μm et sont regroupés en matrices de 4×4 pour former des Cellules, qui sont à leur tour assemblées en Réticules de 32×32. Ces Réticules sont ensuite photo-répétés sur toute la surface d’une tranche de silicium et sont interconnectés entre eux pour former le WaferIC. Cet arrangement particulier de plots conducteurs configurables permet à un usager de déposer sur la surface active du WaferIC les circuits intégrés constituant un système électronique, sans tenir en compte l’orientation spatiale de ces derniers, de créer un schéma d’interconnexions, de distribution la puissance et de débuter le prototypage du système en question. Une version préliminaire a été fabriquées et testées avec succès et permet d’alimenter des circuits -intégrés et de configurer le WaferIC pour les interconnecter. Cette thèse par articles présente une nouvelle version du WaferIC avec une nouvelle proposition de distribution de la puissance avec une approche de maîtres-esclaves qui met en valeur l’utilisation de plusieurs rails d’alimentation afin d’améliorer le rendement énergétique. Il est également mis de l’avant un réseau très dense de convertisseurs analogique-numérique (CAN) et numérique-analogique (CNA) de plus de 300k éléments, tolérant aux défectuosités et aux défauts de fabrication. Ce réseau de CAN-CNA permet d’améliorer le WaferIC avec la transmission de signaux analogiques, en plus des signaux numériques. Ce manuscrit comporte trois articles : un publié chez « Springer Science & Business Media Analog Integrated Circuits and Signal Processing », un publié chez « IEEE Transactions on Circuits and Systems I : Regular Papers » et finalement un soumis chez « IEEE Transactions on Very Large Scale Integration ».----------ABSTRACT Nowadays, electronic systems are in constant growth, size and complexity; combined with time to market it makes a challenge for electronic system designers. A prototyping platform has been recently introduced and addresses all those constraints at once. This platform is based on an active 200 mm in diameter wafer-scale circuit, which is covered with a set of small configurable and conductive pads called NanoPads. These NanoPads are designed to be small enough to support any integrated-circuit μball of a 250 μm diameter and 500 μm of pitch. They are assembled in a 4×4 matrix, forming a Unit-Cell, which are grouped in a Reticle-Image of 32×32. These Reticle-Images are photo-repeated over the entire surface of a 200 mm in diameter wafer and are interconnected together using interreticle stitching. This active wafer-scale circuit is called a WaferIC. This particular topology and distribution of NanoPads allows an electronic system designer to manually deposit any integrated-circuit (IC) on the active alignment insensitive surface of the WaferIC, to build the netlist linking all the ICs, power-up the systems and start the prototyping of the system. In this manuscript-based thesis, we present an improved version of the WaferIC with a novel approach for the power distribution network with a master-slave topology, which makes the use of embedded dual-power-rail voltage regulators in order to improve the power efficiency and decrease thermal dissipation. We also propose a default-tolerant network of analog to digital (ADC) and digital to analog (DAC) converters of more than 300k. This ADC-DAC network allows the WaferIC to not only support digital ICs but also propagate analog signals from one NanoPad to another. This thesis includes 3 papers : one submission to "Springer Science & Business Media Analog Integrated Circuits and Signal Processing", one submission to "IEEE Transactions on Circuits and Systems I : Regular Papers" and finally one submission to "IEEE Transactions on Very Large-Scale Integration". These papers propose novel architectures of dualrail voltage regulators, configurable analog buffers and configurable voltage references, which can be used as a DAC. A novel approach for a power distribution network and the integration of all the presented architectures is also proposed with the fabrication of a testchip in CMOS 0.18 μm technology, which is a small-scale version of the WaferIC