6 research outputs found
PROCESS AWARE ANALOG-CENTRIC SINGLE LEAD ECG ACQUISITION AND CLASSIFICATION CMOS FRONTEND
The primary objective of this research work is the development of a low power single-lead ECG
analog front-end (AFE) architecture which includes acquisition, digitization, process aware efficient
gain and frequency control mechanism and a low complexity classifier for the detecting asystole,
extreme bardycardia and tachycardia. Recent research on ECG recording systems focuses on the
design of a compact single-lead wearable/portable devices with ultra-low-power consumption and
in-built hardware for diagnosis and prognosis. Since, the amplitude of the ECG signal varies from
hundreds of µV to a few mV, and has a bandwidth of DC to 250 Hz, conventional front-ends use
an instrument amplifier followed by a programmable gain amplifier (PGA) to amplify the input
ECG signal appropriately. This work presents an mixed signal ECG fronted with an ultra-low
power two-stage capacitive-coupled signal conditioning circuit (or an AFE), providing programmable
amplification along with tunable 2nd order high pass and lowpass filter characteristics. In the
contemporary state-of-the-art ECG recording systems, the gain of the amplifier is controlled by
external digital control pins which are in turn dynamically controlled through a DSP. Therefore, an
efficient automatic gain control mechanism with minimal area overhead and consuming power in the
order of nano watts only. The AGC turns the subsequent ADC on only after output of the PGA (or
input of the ADC) reaches a level for which the ADC achieves maximum signal-to-noise-ratio (SNR),
hence saving considerable startup power and avoiding the use of DSP. Further, in any practical filter
design, the low pass cut-off frequency is prone to deviate from its nominal value across process
and temperature variations. Therefore, post-fabrication calibration is essential, before the signal
is fed to an ADC, to minimize this deviation, prevent signal degradation due to aliasing of higher
frequencies into the bandwidth
for classification of ECG signals, to switch to low resolution processing, hence saving power and
enhances battery lifetime. Another short-coming noticed in the literature published so far is that
the classification algorithm is implemented in digital domain, which turns out to be a power hungry
approach. Moreover, Although analog domain implementations of QRS complexes detection schemes
have been reported, they employ an external micro-controller to determine the threshold voltage. In
this regard, finally a power-efficient low complexity CMOS fully analog classifier architecture and a
heart rate estimator is added to the above scheme. It reduces the overall system power consumption
by reducing the computational burden on the DSP. The complete proposed scheme consists of (i)
an ultra-low power QRS complex detection circuit using an autonomous dynamic threshold voltage,
hence discarding the need of any external microcontroller/DSP and calibration (ii) a power efficient
analog classifier for the detection of three critical alarm types viz. asystole, extreme bradycardia
and tachycardia. Additionally, a heart rate estimator that provides the number of QRS complexes
within a period of one minute for cardiac rhythm (CR) and heart rate variability (HRV) analysis.
The complete proposed architecture is implemented in UMC 0.18 µm CMOS technology with 1.8 V
supply. The functionality of each of the individual blocks are successfully validated using postextraction
process corner simulations and through real ECG test signals taken from the PhysioNet
database. The capacitive feedback amplifier, Σ∆ ADC, AGC and the AFT are fabricated, and the
measurement results are discussed here. The analog classification scheme is successfully validated
using embed NXP LPC1768 board, discrete peak detector prototype and FPGA software interfac
LOW POWER AND HIGH SIGNAL TO NOISE RATIO BIO-MEDICAL AFE DESIGN TECHNIQUES
The research work described in this thesis was focused on finding novel techniques to
implement a low-power and noise Bio-Medical Analog Front End (BMEF) circuit
technique to enable high-quality Electrocardiography (ECG) sensing. Usually, an ECG
signal and several bio-medical signals are sensed from the human body through a pair
of electrodes. The electrical characteristics of the very small amplitude (1u-10mV)
signals are corrupted by random noise and have a significant dc offset. 50/60Hz power
supply coupling noise is one of the biggest cross-talk signals compared to the thermally
generated random noise. These signals are even AFE composed of an Instrumentation
Amplifier (IA), which will have a better Common Mode rejection ratio (CMRR). The main
function of the AFE is to convert the weak electrical Signal into large signals whose
amplitude is large enough for an Analog Digital Converter (ADC) to detect without having
any errors. A Variable Gain Amplifier (VGA) is sometimes required to adjust signal
amplitude to maintain the dynamic range of the ADC. Also, the Bio-medical transceiver
needs an accurate and temperature-independent reference voltage and current for the
ADC, commonly known as Bandgap Reference Circuit (BGR). These circuits need to
consume as low power as possible to enable these circuits to be powered from the
battery.
The work started with analysing the existing circuit techniques for the circuits
mentioned above and finding the key important improvements required to reach the
target specifications. Previously proposed IA is generated based on voltage mode signal
processing. To improve the CMRR (119dB), we proposed a current mode-based IA with
an embedded DC cancellation technique. State-of-the-art VGA circuits were built based
on the degeneration principle of the differential pair, which will enable the variable gain
purpose, but none of these techniques discussed linearity improvement, which is very
important in modern CMOS technologies. This work enhances the total Harmonic
distortion (THD) by 21dB in the worst case by exploiting the feedback techniques around
the differential pair. Also, this work proposes a low power curvature compensated
bandgap with 2ppm/0C temperature sensitivity while consuming 12.5uW power from a
1.2V dc power supply. All circuits were built in 45nm TSMC-CMOS technology and
simulated with all the performance metrics with Cadence (spectre) simulator. The circuit
layout was carried out to study post-layout parasitic effect sensitivity
High speed IC designs for low power short reach optical links
In this thesis, I have briefly introduced the background of my PhD research, current state-of-the-art design, and my PhD research objectives. Then, I demonstrate how to optimize the performance of PAM-4 transmitters based on lumped Silicon Photonic Mach-Zehnder Modulators (MZMs) for short-reach optical links. Firstly, we analyze the trade-off that occurs between extinction ratio and modulation loss when driving an MZM with a voltage swing less than the MZM’s Vπ. This is important when driver circuits are realized in deep submicron CMOS process nodes. Next, a driving scheme based upon a switched capacitor approach is proposed to maximize the achievable bandwidth of the combined lumped MZM and CMOS driver chip. This scheme allows the use of lumped MZM for high speed optical links with reduced RF driver power consumption compared to the conventional approach of driving MZMs (with transmission line based electrodes) with a power amplifier. This is critical for upcoming short-reach link standards such as 400Gb/s 802.3 Ethernet. The driver chip was fabricated using a 65nm CMOS technology and flip-chipped on top of the Silicon Photonic chip (fabricated using IMEC’s ISIPP25G technology) that contains the MZM. Open eyes with 4dB extinction ratio for a 36Gb/s (18Gbaud) PAM- 4 signal are experimentally demonstrated. The electronic driver chip has a core area of only 0.11mm 2 and consumes 236mW from 1.2V and 2.4V supply voltages. This corresponds to an energy efficiency of 6.55pJ/bit including Gray encoder and retiming, or 5.37pJ/bit for the driver circuit only. In the future, system level analysis should be carried out to investigate the critical pattern issue of the PAM4 optical transmitter. The potential solutions toward 1pJ/bit are given (lumped EAM and micro-ring modulator). In addition, the advanced modulation formats (16 QAM, discrete multitone modulation, and FFE) are presented based on the switched capacitor approach
Low-power high-performance SAR ADC with redundancy and digital background calibration
Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2013.This electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections.Cataloged from student-submitted PDF version of thesis.Includes bibliographical references (p. 195-199).As technology scales, the improved speed and energy eciency make the successive- approximation-register (SAR) architecture an attractive alternative for applications that require high-speed and high-accuracy analog-to-digital converters (ADCs). In SAR ADCs, the key linearity and speed limiting factors are capacitor mismatch and incomplete digital-to-analog converter (DAC)/reference voltage settling. In this the- sis, a sub-radix-2 SAR ADC is presented with several new contributions. The main contributions include investigation of using digital error correction (redundancy) in SAR ADCs for dynamic error correction and speed improvement, development of two new calibration algorithms to digitally correct for manufacturing mismatches, design of new architecture to incorporate redundancy within the architecture itself while achieving 94% better energy eciency compared to conventional switching algorithm, development of a new capacitor DAC structure to improve the SNR by four times with improved matching, joint design of the analog and digital circuits to create an asynchronous platform in order to reach the targeted performance, and analysis of key circuit blocks to enable the design to meet noise, power and timing requirements. The design is fabricated in standard 1P9M 65nm CMOS technology with 1.2V supply. The active die area is 0.083mm² with full rail-to-rail input swing of 2.4V p-p . A 67.4dB SNDR, 78.1dB SFDR, +1.0/-0.9 LSB₁₂ INL and +0.5/-0.7 LSB₁₂ DNL are achieved at 50MS/s at Nyquist rate. The total power consumption, including the estimated calibration and reference power, is 2.1mW, corresponding to 21.9fJ/conv.- step FoM. This ADC achieves the best FoM of any ADCs with greater than 10b ENOB and 10MS/s sampling rate.by Albert Hsu Ting Chang.Ph.D