Integrated Circuits for Programming Flash Memories in Portable Applications

Smart devices such as smart grids, smart home devices, etc. are infrastructure systems that connect the world around us more than before. These devices can communicate with each other and help us manage our environment. This concept is called the Internet of Things (IoT). Not many smart nodes exist that are both low-power and programmable. Floating-gate (FG) transistors could be used to create adaptive sensor nodes by providing programmable bias currents. FG transistors are mostly used in digital applications like Flash memories. However, FG transistors can be used in analog applications, too. Unfortunately, due to the expensive infrastructure required for programming these transistors, they have not been economical to be used in portable applications. In this work, we present low-power approaches to programming FG transistors which make them a good candidate to be employed in future wireless sensor nodes and portable systems. First, we focus on the design of low-power circuits which can be used in programming the FG transistors such as high-voltage charge pumps, low-drop-out regulators, and voltage reference cells. Then, to achieve the goal of reducing the power consumption in programmable sensor nodes and reducing the programming infrastructure, we present a method to program FG transistors using negative voltages. We also present charge-pump structures to generate the necessary negative voltages for programming in this new configuration

High Performance Power Management Integrated Circuits for Portable Devices

abstract: Portable devices often require multiple power management IC (PMIC) to power different sub-modules, Li-ion batteries are well suited for portable devices because of its small size, high energy density and long life cycle. Since Li-ion battery is the major power source for portable device, fast and high-efficiency battery charging solution has become a major requirement in portable device application. In the first part of dissertation, a high performance Li-ion switching battery charger is proposed. Cascaded two loop (CTL) control architecture is used for seamless CC-CV transition, time based technique is utilized to minimize controller area and power consumption. Time domain controller is implemented by using voltage controlled oscillator (VCO) and voltage controlled delay line (VCDL). Several efficiency improvement techniques such as segmented power-FET, quasi-zero voltage switching (QZVS) and switching frequency reduction are proposed. The proposed switching battery charger is able to provide maximum 2 A charging current and has an peak efficiency of 93.3%. By configure the charger as boost converter, the charger is able to provide maximum 1.5 A charging current while achieving 96.3% peak efficiency. The second part of dissertation presents a digital low dropout regulator (DLDO) for system on a chip (SoC) in portable devices application. The proposed DLDO achieve fast transient settling time, lower undershoot/overshoot and higher PSR performance compared to state of the art. By having a good PSR performance, the proposed DLDO is able to power mixed signal load. To achieve a fast load transient response, a load transient detector (LTD) enables boost mode operation of the digital PI controller. The boost mode operation achieves sub microsecond settling time, and reduces the settling time by 50% to 250 ns, undershoot/overshoot by 35% to 250 mV and 17% to 125 mV without compromising the system stability.Dissertation/ThesisDoctoral Dissertation Electrical Engineering 201

Design methodology for reliable and energy efficient self-tuned on-chip voltage regulators

The energy-efficiency needs in computing systems, ranging from high performance processors to low-power devices is steadily on the rise, resulting in increasing popularity of on-chip voltage regulators (VR). The high-frequency and high bandwidth on-chip voltage regulators such as Inductive voltage regulators (IVR) and Digital Low Dropout regulators (DLDO) significantly enhance the energy-efficiency of a SoC by reducing supply noise and enabling faster voltage transitions. However, IVRs and DLDOs need to cope with the higher variability that exists in the deep nanometer digital nodes since they are fabricated on the same die as the digital core affecting performance of both the VR and digital core. Moreover, in most modern SoCs where multiple power domains are preferred, each VR needs to be designed and optimized for a target load demand which significantly increases the design time and time to market for VR assisted SoCs. This thesis investigates a performance-based auto-tuning algorithm utilizing performance of digital core to tune VRs against variations and improve performance of both VR and the core. We further propose a fully synthesizable VR architecture and an auto-generation tool flow that can be used to design and optimize a VR for given target specifications and auto-generate a GDS layout. This would reduce the design time drastically. And finally, a flexible precision IVR architecture is also explored to further improve transient performance and tolerance to process variations. The proposed IVR and DLDO designs with an AES core and auto-tuning circuits are prototyped in two testchips in 130nm CMOS process and one test chip in 65nm CMOS process. The measurements demonstrate improved performance of IVR and AES core due to performance-based auto-tuning. Moreover, the synthesizable architectures of IVR and DLDO implemented using auto-generation tool flow showed competitive performance with state of art full custom designs with orders of magnitude reduction in design time. Additional improvement in transient performance of IVR is also observed due to the flexible precision feedback loop design.Ph.D

An accurate, trimless, high PSRR, low-voltage, CMOS bandgap reference IC

Bandgap reference circuits are used in a host of analog, digital, and mixed-signal systems to establish an accurate voltage standard for the entire IC. The accuracy of the bandgap reference voltage under steady-state (dc) and transient (ac) conditions is critical to obtain high system performance. In this work, the impact of process, power-supply, load, and temperature variations and package stresses on the dc and ac accuracy of bandgap reference circuits has been analyzed. Based on this analysis, the a bandgap reference that 1. has high dc accuracy despite process and temperature variations and package stresses, without resorting to expensive trimming or noisy switching schemes, 2. has high dc and ac accuracy despite power-supply variations, without using large off-chip capacitors that increase bill-of-material costs, 3. has high dc and ac accuracy despite load variations, without resorting to error-inducing buffers, 4. is capable of producing a sub-bandgap reference voltage with a low power-supply, to enable it to operate in modern, battery-operated portable applications, 5. utilizes a standard CMOS process, to lower manufacturing costs, and 6. is integrated, to consume less board space has been proposed. The functionality of critical components of the system has been verified through prototypes after which the performance of the complete system has been evaluated by integrating all the individual components on an IC. The proposed CMOS bandgap reference can withstand 5mA of load variations while generating a reference voltage of 890mV that is accurate with respect to temperature to the first order. It exhibits a trimless, dc 3-sigma accuracy performance of 0.84% over a temperature range of -40°C to 125°C and has a worst case ac power-supply ripple rejection (PSRR) performance of 30dB up to 50MHz using 60pF of on-chip capacitance. All the proposed techniques lead to the development of a CMOS bandgap reference that meets the low-cost, high-accuracy demands of state-of-the-art System-on-Chip environments.Ph.D.Committee Chair: Rincon-Mora, Gabriel; Committee Member: Ayazi, Farrokh; Committee Member: Bhatti, Pamela; Committee Member: Leach, W. Marshall; Committee Member: Morley, Thoma

Wireless Personal Area Network-Based Assistance for the Visually Impaired

In this dissertation, a system allowing a visually impaired person to interact with his environment is developed using modern, low-power wireless communications techniques. With recent advances in wireless sensor networks, open-source operating systems, and embedded processing technology, low-cost devices have become practically feasible as a personal notification system for impaired people. Additionally, text-to-speech capabilities can now be employed without special application specific integrated circuits (ASICs), allowing low-cost, general-purpose processors to fill a niche that once required expensive semiconductors. The system takes advantage of 802.15.4 and media access control (MAC) protocols offered by the open source operating system TinyOS. Important characteristics of these new standards that make them ideal for interface with humans are short range, low- power, and open-source software. To facilitate research and development in use and integration of such devices, we developed a hardware platform to allow exploration of possible future network architectures with multiple options for interfacing with the user. Our Visually Impaired Notification System (VINS) allows unprecedented awareness of the environment and has been simulated with multiple nodes using a modification of the TinyOS Dissemination protocol. This dissertation outlines the hardware platform, demonstration of a working prototype, and simulations of how the system would work in its intended environment. We envision this system being used as a testbed allowing further research of other communications and message-delivery techniques. Additionally, the research has contributed directly to the TinyOS project and offered new insight into power management in embedded systems. Finally, through the research effort we were able to contribute to the open source movement and have produced software in four languages used in three countries with over 1500 downloads

Rural Facility Electric Power Quality Enhancement

Electric power disturbances are known to be more prevalent in small, isolated power systems than in larger interconnected grids which service most of the United States. This fact has given rise to a growing concern about the relative merits of different types of power conditioning equipment and their effectiveness in protecting sensitive electronics and essential loads in rural Alaska. A study has been conducted which compares isolation transformers, voltage regulators, power conditioners, uninterruptible power supplies and indoor computer surge suppressors in their ability to suppress the various disturbances which have been measured in several Alaskan communities. These include voltage sags and surges, impulses, blackouts, frequency variations and long-term voltage abnormalities. In addition, the devices were also subjected to fast, high-magnitude impulses such as might be expected in the event of a lightning strike to or near utility distribution equipment. The solutions for power line problems will vary for different load applications and for different rural electrical environments. The information presented in this report should prove to be valuable in making the analysis.List of Figures - viii List of Tables - xiv Acknowledgements - xv Chapter 1: Electric Disturbances in Power Systems Introduction - 16 Categorizing Electrical Disturbances - 17 Voltage Disturbances and Transients - 19 Frequency Disturbances - 22 Sources of Transients - 22 Lightning and EMP - 23 Switching - 24 Power System Noise - 25 Common Mode and Normal Mode Noise Signals - 26 Chapter 2: Power Quality in Rural Alaska Characterizing the Village Power System - 28 The Village Electric Load - 29 Power Quality Site Surveys - 30 Rural Power Quality in Alaska - 31 Power Conditioning Requirements for Village Loads - 37 Chapter 3: Isolation, Voltage Regulation and Power Conditioning Introduction - 39 Slow Voltage Fluctuations - 39 Voltage Regulation and Power Conditioning - 40 Ferroresonant Transformers - 40 Electronic Tap-Changing Regulators - 44 Isolation Transformers - 47 Dedicated Lines - 51 Chapter 4: Impulse Suppression Introduction - 52 Surge Suppressors - 52 Surge Suppressor Components - 55 Component Configuration - 58 EMI/RFI Filters - 58 Standard Tests for Evaluating Surge Suppressor Performance - 60 Scope of Impulse Testing for Rural Alaska - 60 Impulse Test Equipment - 62 Test Procedure - 62 Impulse Testing Measurements - 63 Test Results - 64 Chapter 5: Uninterruptible Power Supplies The True UPS - 68 Standby Power Systems and a New Generation of UPS - 69 UPS Backup Time - 74 UPS Testing - 74 Chapter 6: Computers and Power Problems Introduction - 78 The Computer Tolerance Envelope - 78 Ridethrough - 80 Component Degradation and Equipment Failure - 82 Computer Power Supplies - 82 Linear Power Supplies - 83 Switching Power Supplies - 84 PC Tolerance of Powerline Disturbances - 84 Chapter 7: Comparing Power Conditioning Alternatives Voltage Regulation - 89 Isolation - 93 Uninterruptible Power Systems - 94 Computer Surge Suppressors - 98 Summary - 98 Appendices Appendix A: Voltage Clamping Levels of Surge Suppressors - 101 Appendix B: Voltage Clamping Levels of Power Conditioners and Uninterruptible Power Systems - 115 Appendix C: Noise Suppression of Surge Suppressors and Power Conditioners - 129 Appendix D: Waveforms and Regulating Characteristics of Power Conditioners and Uninterruptible Power Systems - 135 Appendix E: Comparison of Voltage Clamping Levels of Surge Suppressors Power Conditioners, Isolation Transformers and Uninterruptible Power Systems to High-Magnitude Impulse Voltages - 151 References - 16

A compact high-energy particle detector for low-cost deep space missions

Over the last few decades particle physics has led to many new discoveries, laying the foundation for modern science. However, there are still many unanswered questions which the next generation of particle detectors could address, potentially expanding our knowledge and understanding of the Universe. Owing to recent technological advancements, electronic sensors are now able to acquire measurements previously unobtainable, creating opportunities for new deep-space high-energy particle missions. Consequently, a new compact instrument was developed capable of detecting gamma rays, neutrons and charged particles. This instrument combines the latest in FPGA System-on-Chip technology as the central processor and a 3x3 array of silicon photomultipliers coupled with an organic plastic scintillator as the detector. Using modern digital pulse shape discrimination and signal processing techniques, the scintillator and photomultiplier combination has been shown to accurately discriminate between the di_erent particle types and provide information such as total energy and incident direction. The instrument demonstrated the ability to capture 30,000 particle events per second across 9 channels - around 15 times that of the U.S. based CLAS detector. Furthermore, the input signals are simultaneously sampled at a maximum rate of 5 GSPS across all channels with 14-bit resolution. Future developments will include FPGA-implemented digital signal processing as well as hardware design for small satellite based deep-space missions that can overcome radiation vulnerability

Analysis on Supercapacitor Assisted Low Dropout (SCALDO) Regulators

State-of-the-art electronic systems employ three fundamental techniques for DC-DC converters: (a) switch-mode power supplies (SMPS); (b) linear power supplies; (c) switched capacitor (charge pump) converters. In practical systems, these three techniques are mixed to provide a complex, but elegant, overall solution, with energy efficiency, effective PCB footprint, noise and transient performance to suit different electronic circuit blocks. Switching regulators have relatively high end-to-end efficiency, in the range of 70 to 93%, but can have issues with output noise and EMI/RFI emissions. Switched capacitor converters use a set of capacitors for energy storage and conversion. In general, linear regulators have low efficiencies in the range 30 to 60%. However, they have outstanding output characteristics such as low noise, excellent transient response to load current fluctuations, design simplicity and low cost design which are far superior to SMPS. Given the complex situation in switch-mode converters, low dropout (LDO) regulators were introduced to address the equirements of noise-sensitive and fast transient loads in portable devices. A typical commercial off-the-shelf LDO has its input voltage slightly higher than the desired regulated output for optimal efficiency. The approximate efficiency of a linear regulator, if the power consumed by the control circuits is negligible, can be expressed by the ratio of Vo/Vin. A very low frequency supercapacitor circulation technique can be combined with commercial low dropout regulator ICs to significantly increase the end-to-end efficiency by a multiplication factor in the range of 1.33 to 3, compared to the efficiency of a linear regulator circuit with the same input-output voltages. In this patented supercapacitor-assisted low dropout (SCALDO) regulator technique developed by a research team at the University of Waikato, supercapacitors are used as lossless voltage droppers, and the energy reuse occurs at very low frequencies in the range of less than ten hertz, eliminating RFI/EMI concerns. This SCALDO technique opens up a new approach to design step-down, DC-DC converters suitable for processor power supplies with very high end-to-end efficiency which is closer to the efficiencies of practical switching regulators, while maintaining the superior output specifications of a linear design. Furthermore, it is important to emphasize that the SCALDO technique is not a variation of well-known switched capacitor DC-DC converters. In this thesis, the basic SCALDO concept is further developed to achieve generalised topologies, with the relevant theory that can be applied to a converter with any input-output step-down voltage combination. For these generalised topologies, some important design parameters, such as the number of supercapacitors, switching matrix details and efficiency improvement factors, are derived to form the basis of designing SCALDO regulators. With the availability of commercial LDO ICs with output current ratings up to 10 A, and thin-prole supercapacitors with DC voltage ratings from 2.3 to 5.5 V, several practically useful, medium-current SCALDO prototypes: 12V-to-5V, 5V-to-2V, 5.5V-to-3.3V have been developed. Experimental studies were carried out on these SCALDO prototypes to quantify performance in terms of line regulation, load regulation, efficiency and transient response. In order to accurately predict the performance and associated waveforms of the individual phases (charge, discharge and transition) of the SCALDO regulator, Laplace transform-based theory for supercapacitor circulation is developed, and analytical predictions are compared with experimental measurements for a 12V-to-5V prototype. The analytical results tallied well with the practical waveforms observed in a 12V-to-5V converter, indicating that the SCALDO technique can be generalized to other versatile configurations, and confirming that the simplified assumptions used to describe the circuit elements are reasonable and justifiable. After analysing the performance of several SCALDO prototypes, some practical issues in designing SCALDO regulators have been identified. These relate to power losses and implications for future development of the SCALDO design