An all monolithic MOS A/D converter - Low power clocks, multiplexers, registers, and A/D converter Final report

Research and developments of monolithic, MOS, ten bit, analog to digital converte

Hybrid A/D converter for 200 deg C operation

A 12 bit A/D converter was designed and developed which will operate at 200 C with .05 linearity, 1/accuracy, 350 WSec conversion time, and only 455 mW power consumption. This product also necessitated the development of a unique three metal system in which aluminum wire bonding is done utilizing aluminum bonding pads, gold wire bonding to all gold areas, and employment of a nickel interface between gold and aluminum connections. This system totally eliminates the formation of a intermetallics at the bonding interface which can lead to bond failure. This product represents an advancement in electronics as it proved the operation of integrated circuits at high temperature, as well as providing information about both the electrical and mechanical reliability of hybrid circuits at 200 C

RANCANG BANGUN A/D CONVERTER MENGGUNAKAN MODULATOR SIGMA DELTA DUA INTEGRATOR

ABSTRAKSI: Modulator Sigma Delta ( ) merupakan suatu modulator pulsa dengan komponen dasar terdiri dari Integrator ( ) dan penyelisih ( ) yang dapat mengubah sinyal analog menjadi sinyal digital dengan keluaran secara serial, sehingga modulator ini seringkali disebut juga A/D (Analog to Digital) Converter Sigma Delta. Pada prisipnya Modulator Sigma Delta ini menggunakan teknik Oversampling dan konsep Noise Shaping. Dimana Oversampling merupakan teknik pencuplikan sinyal dengan menggunakan frekuensi sampling yang nilainya lebih besar daripada frekuensi sampling menurut kriteria Nyquist. Sedangkan Noise Shaping merupakan suatu kinerja dari rangkaian yang menyebabkan noise kuantisasi akan tersebar di frekuensi lebih tinggi dari frekuensi sinyal informasinya sehingga mengurangi level noise kuantisasi di baseband. Dengan teknik Oversampling dan Noise Shaping maka nilai SNR (Signal to Noise Ratio) yang dihasilkan akan lebih baikPada Proyek Akhir ini telah dirancang dan implementasikan suatu Modulator Sigma Delta secara simulasi dan hardware untuk mengubah suara manusia (speech) sebagai sinyal informasi dengan memilih frekuensi sebesar 3 KHz yang kemudian mengubah sinyal tersebut menjadi sinyal digital dengan kecepatan 64 KBps. Modulator Sigma Delta yang dimplementasikan pada proyek akhir ini terdiri dari dua rangkaian penyelisih, dua integrator berfungsi sebagai Noise Shaping, sebuah DAC 1-bit sebagai penghasil sinyal feedback, sebuah komparator 1-bit sebagai pengkuantisasi diikuti oleh D flip-flop dan generator pulsa yang berfungsi sebagai pencuplik.Realisasi alat yang telah dilakukan menghasilkan suatu sinyal digital serial 64 KBps yang mengikuti karakteristik dari sinyal informasi dengan frekuensi terukur sebesar 64,10 KHz dengan tegangan puncak ke puncak sebesar 4,437 volt serta menghasilkan SNR sebesar 32,6 dB.Kata Kunci : ADC, Converter, Sigma, Delta, ModulatorABSTRACT: Sigma Delta Modulator ( ) is an analog pulse modulator which basic components are Integrator ( ) and Difference Circuit ( ) that makes an analog become a digital signal with the serial output, so from this modulator definiton usually called an A/D (Analog to Digital) Converter Sigma Delta. The principle of Sigma Delta Modulator based on some methods called Oversampling and Noise Shaping concept. The technique of Oversampling is a sampling method by using sampling frequency which the rate more higher than the sampling frequency if using Nyquist criteria. While, Noise Shaping is an effect of the circuit that can makes the quantization noise spread on higher frequency from the information signal, so it can decrease the quantization noise in baseband level. By using Oversampling and Noise Shaping, the SNR (Signal to Noise Ratio) which produced can be improved.This final project of Sigma Delta Modulator had already designed and implemented on a simulation and hardware to change human voice (speech) as signal information which choosen in frequency 3 KHz, then change this signal become a digital signal which speed 64 KBps. The Sigma Delta Modulator that implemented on this final project are consist of two difference circuits, two integrators which function as a Noise Shaping, a DAC 1-bit which produced feedback signal, a Comparator 1-bit as a quantizer followed by D flip-flop, and a pulse generator which function as a sampling circuit.The realization of this device that have been done, produced a digital signal 64 KBps which the output follows the characteristic of the information signal with the value of measured frequency is 64,10 KHz, 4,437 Volts Peak to Peak voltage ,and 32,6 dB SNR .Keyword: ADC, Converter, Sigma, Delta, Modulato

An HTS Quasi-One junction SQUID-based periodic threshold comparator for a 4-bit superconductive flash A/D converter

An all high-Tc periodic threshold comparator for application in a 4-bit superconductive A/D converter has been realized and tested. The theoretical threshold curve of the comparator is calculated and compared to the measured results. Furthermore, the thermal noise immunity and the influence of flux-flow are considered, resulting in practical design constraints for the comparator circui

Developing Model-Based Design Evaluation for Pipelined A/D Converters

This paper deals with a prospective approach of modeling, design evaluation and error determination applied to pipelined A/D converter architecture. In contrast with conventional ADC modeling algorithms targeted to extract the maximum ADC non-linearity error, the innovative approach presented allows to decompose magnitudes of individual error sources from a measured or simulated response of an ADC device. Design Evaluation methodology was successfully applied to Nyquist rate cyclic converters in our works [13]. Now, we extend its principles to pipelined architecture. This qualitative decomposition can significantly contribute to the ADC calibration procedure performed on the production line in term of integral and differential nonlinearity. This is backgrounded by the fact that the knowledge of ADC performance contributors provided by the proposed method helps to adjust the values of on-chip converter components so as to equalize (and possibly minimize) the total non-linearity error. In this paper, the design evaluation procedure is demonstrated on a system design example of pipelined A/D converter. Significant simulation results of each stage of the design evaluation process are given, starting from the INL performance extraction proceeded in a powerful Virtual Testing Environment implemented in Maple™ software and finishing by an error source simulation, modeling of pipelined ADC structure and determination of error source contribution, suitable for a generic process flow

Microprocessor-based single particle calibration of scintillation counter

A microprocessor-base set-up is fabricated and tested for the single particle calibration of the plastic scintillator. The single particle response of the scintillator is digitized by an A/D converter, and a 8085 A based microprocessor stores the pulse heights. The digitized information is printed. Facilities for CRT display and cassette storing and recalling are also made available

Investigation of critical slowing down in a bistable S-SEED

A simulation of S-SEED switching based upon experimental data is developed that includes the effect of critical slowing down. The simulation's accuracy is demonstrated by close agreement with the results from experimental S-SEED switching. The simulation is subsequently used to understand how the phenomenon of critical slowing down applies to switching of an S-SEED and how the effect on photonic analog-to-digital (A/D) converter performance may be minimized.B. A. Clare, K. A. Corbett, K. J. Grant, P. B. Atanackovic, W. Marwood and J. Munc