Optimization of Electrical Validation and Debug Time in Reference Clocks

La Validación Eléctrica y depuración, a nivel de sistema, de las señales de reloj de referencia, requiere muchos conocimientos y habilidades de Integridad de Señal y Alta Frecuencia. La intención de este trabajo es mejorar la metodología de validación actual e incrementar el conocimiento técnico, de esta manera nuestro equipo de validación podrá encontrar defectos y causas raíz rápidamente. Estaremos analizando, modelando y simulando los principales cuatro casos de depuración vistos en los ciclos de validación anteriores, diseñando y utilizando búferes de reloj con impedancia controlada, así como líneas de transmisión. El resultado obtenido es que, aparte de haber creado habilidades y conocimiento, también estamos observando muy buena correlación entre la simulación y el comportamiento real de nuestros productos

CMOS Transmitter using Pulse-Width Modulation Pre-Emphasis achieving 33dB Loss Compensation at 5-Gb/s

A digital transmitter pre-emphasis technique is presented that is based on pulse-width modulation, instead of finite impulse response (FIR) filtering. The technique fits well to future high-speed low-voltage CMOS processes. A 0.13 /spl mu/m CMOS transmitter achieves more than 5 Gb/s (2-PAM) over 25 m of standard RG-58U low-end coaxial copper cable. The test chip compensates for up to 33 dB of channel loss at the fundamental signaling frequency (2.5 GHz), which is the highest figure compared to literature

Power Reductions with Energy Recovery Using Resonant Topologies

The problem of power densities in system-on-chips (SoCs) and processors has become more exacerbated recently, resulting in high cooling costs and reliability issues. One of the largest components of power consumption is the low skew clock distribution network (CDN), driving large load capacitance. This can consume as much as 70% of the total dynamic power that is lost as heat, needing elaborate sensing and cooling mechanisms. To mitigate this, resonant clocking has been utilized in several applications over the past decade. An improved energy recovering reconfigurable generalized series resonance (GSR) solution with all the critical support circuitry is developed in this work. This LC resonant clock driver is shown to save about 50% driver power (\u3e40% overall), on a 22nm process node and has 50% less skew than a non-resonant driver at 2GHz. It can operate down to 0.2GHz to support other energy savings techniques like dynamic voltage and frequency scaling (DVFS). As an example, GSR can be configured for the simpler pulse series resonance (PSR) operation to enable further power saving for double data rate (DDR) applications, by using de-skewing latches instead of flip-flop banks. A PSR based subsystem for 40% savings in clocking power with 40% driver active area reduction xii is demonstrated. This new resonant driver generates tracking pulses at each transition of clock for dual edge operation across DVFS. PSR clocking is designed to drive explicit-pulsed latches with negative setup time. Simulations using 45nm IBM/PTM device and interconnect technology models, clocking 1024 flip-flops show the reductions, compared to non-resonant clocking. DVFS range from 2GHz/1.3V to 200MHz/0.5V is obtained. The PSR frequency is set \u3e3× the clock rate, needing only 1/10th the inductance of prior-art LC resonance schemes. The skew reductions are achieved without needing to increase the interconnect widths owing to negative set-up times. Applications in data circuits are shown as well with a 90nm example. Parallel resonant and split-driver non-resonant configurations as well are derived from GSR. Tradeoffs in timing performance versus power, based on theoretical analysis, are compared for the first time and verified. This enables synthesis of an optimal topology for a given application from the GSR

Radio Properties of the Auroral Ionosphere, Final Report (Phase I)

It has been found in recent years that a study of the fluctuations in the signals received from radio stars affords a powerful means of investigating the irregular structure of the ionosphere. In 1955 studies of this type, using frequencies of 223 Me and 456 Me, were initiated at the Geophysical Institute, with a view to investigating the smallscale structure of the highly disturbed auroral ionosphere. The purpose of this report is to present a complete description of the initial experimental arrangement. Further developments of the equipment and some results of analysis of the data have been presented in Quarterly Progress Reports covering the period since 1 June 1956, The report is divided into three sections. Section I contains a description of the basic philosophy of the experiment with an elementary discussion of the various parameters involved. Section II contains a brief description of the actual field installation, and Section III is devoted to the electronic design features. The diagrams pertaining to each section are located at the end of the section.Air Force Contract No. AF 30(635)-2887 Project No. 5535 - Task 45774 Rome Air Development Center, Griffiss Air Force Base Rome, New YorkABSTRACT AND GENERAL INTRODUCTION -- [SECTION I] Investigation of the Ionosphere Using Extra- Terrestrial Radio Sources : 1.1 Introduction ; 1.2 Extra-Terrestrial Sources ; Apparent Positions ; 1.3 Instrumental Techniques for the Study of Radiation from Radio Stars ; Interferometer Methods ; Advantages of the Phase-Switch Interferometer ; Interferometer Parameters ; 1.5 Limitations on Accuracy -- References -- [SECTION II] The Field Installation : 2.1 Introduction ; 2.2 The Radio Telescope Towers ; 2.3 The Antennas ; 2.4 Acknowledgements -- [SECTION III] Electronic Design of Phase-Switch Interferometers : 3.1 Introduction ; 3.2 223 Mc Phase-Switch Equipment ; 3.3 456 Mc Phase-Switch Equipment ; 3.4 Auxiliary EquipmentYe

Predictive control for energy management in all/more electric vehicles with multiple energy storage units

The paper describes the application of Model Predictive Control (MPC) methodologies for application to electric and hybrid-electric vehicle drive-train formats incorporating multiple energy/power sources. Particular emphasis is given to the co-ordinated management of energy flow from the multiple sources to address issues of extended vehicle range and battery life-time for all-electric drive-trains, and emissions reduction and drive-train torsional oscillations, for hybrid-electric counterparts, whilst accommodating operational constraints and, ultimately, generic non-standard driving cycles

A Novel Boost Converter Based LED Driver Chip Targeting Mobile Applications

abstract: A novel integrated constant current LED driver design on a single chip is developed in this dissertation. The entire design consists of two sections. The first section is a DC-DC switching regulator (boost regulator) as the frontend power supply; the second section is the constant current LED driver system. In the first section, a pulse width modulated (PWM) peak current mode boost regulator is utilized. The overall boost regulator system and its related sub-cells are explained. Among them, an original error amplifier design, a current sensing circuit and slope compensation circuit are presented. In the second section – the focus of this dissertation – a highly accurate constant current LED driver system design is unveiled. The detailed description of this highly accurate LED driver system and its related sub-cells are presented. A hybrid PWM and linear current modulation scheme to adjust the LED driver output currents is explained. The novel design ideas to improve the LED current accuracy and channel-to-channel output current mismatch are also explained in detail. These ideas include a novel LED driver system architecture utilizing 1) a dynamic current mirror structure and 2) a closed loop structure to keep the feedback loop of the LED driver active all the time during both PWM on-duty and PWM off-duty periods. Inside the LED driver structure, the driving amplifier with a novel slew rate enhancement circuit to dramatically accelerate its response time is also presented.Dissertation/ThesisDoctoral Dissertation Electrical Engineering 201

Designing YIG Drivers

Design aspects of a linear, stabilized voltage to current transducer for driving YIG tuned microwave devices are analysed. Typical circuits with OP AMP interfacial input and bipolar/VMOS current amplifier outputs are sketched. Attention is drawn to such circuit refinements as (i) augmenting differentiator for minimising sweep delay; (ii) linearizer to compensate for nonlinearity due to core saturation; and (iii) low noise, low drift and minimal voltage pushing options