CIRCUIT MODULES FOR BROADBAND CMOS SIX-PORT SYSTEMS

This dissertation investigates four circuit modules used in a CMOS integrated six-port measurement system. The first circuit module is a wideband power source generator, which can be implemented with a voltage controlled ring oscillator. The second circuit module is a low-power 0.5 GHz - 20.5 GHz power detector with an embedded amplifier and a wideband quasi T-coil matching network. The third circuit module is a six-port circuit, which can be implemented with distributed or lumped- lement techniques. The fourth circuit module is the phase sifter used as calibration loads. The theoretical analysis, circuit design, simulated or experimental verifications of each circuit module are also included

A 300-800MHz Tunable Filter and Linearized LNA applied in a Low-Noise Harmonic-Rejection RF-Sampling Receiver

A multiband flexible RF-sampling receiver aimed at software-defined radio is presented. The wideband RF sampling function is enabled by a recently proposed discrete-time mixing downconverter. This work exploits a voltage-sensing LNA preceded by a tunable LC pre-filter with one external coil to demonstrate an RF-sampling receiver with low noise figure (NF) and high harmonic rejection (HR). The second-order LC filter provides voltage pre-gain and attenuates the source noise aliasing, and it also improves the HR ratio of the sampling downconverter. The LNA consists of a simple amplifier topology built from inverters and resistors to improve the third-order nonlinearity via an enhanced voltage mirror technique. The RF-sampling receiver employs 8 times oversampling covering 300 to 800 MHz in two RF sub-bands. The chip is realized in 65 nm CMOS and the measured gain across the band is between 22 and 28 dB, while achieving a NF between 0.8 to 4.3 dB. The IIP2 varies between +38 and +49 dBm and the IIP3 between -14 dBm and -9 dBm, and the third and fifth order HR ratios are more than 60 dB. The LNA and downconverter consumes 6 mW, and the clock generator takes 12 mW at 800 MHz RF.\ud \u

A 0.1–5.0 GHz flexible SDR receiver with digitally assisted calibration in 65 nm CMOS

© 2017 Elsevier Ltd. All rights reserved.A 0.1–5.0 GHz flexible software-defined radio (SDR) receiver with digitally assisted calibration is presented, employing a zero-IF/low-IF reconfigurable architecture for both wideband and narrowband applications. The receiver composes of a main-path based on a current-mode mixer for low noise, a high linearity sub-path based on a voltage-mode passive mixer for out-of-band rejection, and a harmonic rejection (HR) path with vector gain calibration. A dual feedback LNA with “8” shape nested inductor structure, a cascode inverter-based TCA with miller feedback compensation, and a class-AB full differential Op-Amp with Miller feed-forward compensation and QFG technique are proposed. Digitally assisted calibration methods for HR, IIP2 and image rejection (IR) are presented to maintain high performance over PVT variations. The presented receiver is implemented in 65 nm CMOS with 5.4 mm2 core area, consuming 9.6–47.4 mA current under 1.2 V supply. The receiver main path is measured with +5 dB m/+5dBm IB-IIP3/OB-IIP3 and +61dBm IIP2. The sub-path achieves +10 dB m/+18dBm IB-IIP3/OB-IIP3 and +62dBm IIP2, as well as 10 dB RF filtering rejection at 10 MHz offset. The HR-path reaches +13 dB m/+14dBm IB-IIP3/OB-IIP3 and 62/66 dB 3rd/5th-order harmonic rejection with 30–40 dB improvement by the calibration. The measured sensitivity satisfies the requirements of DVB-H, LTE, 802.11 g, and ZigBee.Peer reviewedFinal Accepted Versio

Microwave CMOS VCOs and Front-Ends - using integrated passives on-chip and on-carrier

The increasing demand for high data rates in wireless communication systems is increasing the requirements on the transceiver front-ends, as they are pushed to utilize more and wider bands at higher frequencies. The work in this thesis is focused on receiver front-ends composed of Low Noise Amplifiers (LNAs), Mixers, and Voltage Controlled Oscillators (VCOs) operating at microwave frequencies. Traditionally, microwave electronics has used exclusive and more expensive semiconductor technologies (III-V materials). However, the rapid development of consumer electronics (e.g. video game consoles) the last decade has pushed the silicon CMOS IC technology towards even smaller feature sizes. This has resulted in high speed transistors (high fT and fmax) with low noise figures. However, as the breakdown voltages have decreased, a lower supply voltage must be used, which has had a negative impact on linearity and dynamic range. Nonetheless, todays downscaled CMOS technology is a feasible alternative for many microwave and even millimeter wave applications. The low quality factor (Q) of passive components on-chip usually limits the high frequency performance. For inductors realized in a standard CMOS process the substrate coupling results in a degraded Q. The quality factor can, however, be improved by moving the passive components off-chip and integrating them on a low loss carrier. This thesis therefore features microwave front-end and VCO designs in CMOS, where some designs have been flip-chip mounted on carriers featuring high Q inductors and low loss baluns. The thesis starts with an introduction to wireless communication, receiver architectures, front-end receiver blocks, and low loss carrier technology, followed by the included papers. The six included papers show the capability of CMOS and carrier technology at microwave frequencies: Papers II, III, and VI demonstrate fully integrated CMOS circuit designs. An LC-VCO using an accumulation mode varactor is presented in Paper II, a QVCO using 4-bit switched tuning is shown in Paper III, and a quadrature receiver front-end (including QVCO) is demonstrated in paper VI. Papers I and IV demonstrate receiver front-ends using low loss baluns on carrier for the LO and RF signals. Paper IV also includes a front-end using single-ended RF input which is converted to differential form in a novel merged LNA and balun. A VCO demonstrating the benefits of a high Q inductor on carrier is presented in Paper V

High Frequency Devices and Circuit Modules for Biochemical Microsystems

This dissertation investigates high frequency devices and circuit modules for biochemical microsystems. These modules are designed towards replacing external bulky laboratory instruments and integrating with biochemical microsystems to generate and analyze signals in frequency and time domain. The first is a charge pump circuit with modified triple well diodes, which is used as an on-chip power supply. The second is an on-chip pulse generation circuit to generate high voltage short pulses. It includes a pulse-forming-line (PFL) based pulse generation circuit, a Marx generator and a Blumlein generator. The third is a six-port circuit based on four quadrature hybrids with 2.0~6.0 GHz operating frequency tuning range for analyzing signals in frequency domain on-chip. The fourth is a high-speed sample-and-hold circuit (SHC) with a 13.3 Gs/s sampling rate and ~11.5 GHz input bandwidth for analyzing signals in time domain on-chip. The fifth is a novel electron spin resonance (ESR) spectroscopy with high-sensitivity and wide frequency tuning range

A reconfigurable 60GHz receiver : providing robustness to process variations

The problems associated with process-induced variability and other challenges of 60GHz circuit design and measurement are treated in this thesis. A system-level analysis is performed on a generic RF receiver. For doing that, first, bit error rate (BER) is considered as a figure of merit representing the overall performance of the Receiver. Then, each stage of the receiver is described by three parameters: voltage gain, noise, and nonlinearity which are prone to variation due to process spread. The variation of these parameters represents all lower-level sources of variability. Since bit error rate (BER), as a major performance measure of the receiver, is a direct function of the noise and distortion, the contribution of each block to the overall noise plus distortion (NPD) is analyzed, which opens the way for minimization of the sensitivity of the NPD to the performance variation of individual stages. It is shown that the first order sensitivities of NPD to the individual gains of the building blocks can all be made zero. Its second order sensitivity to the gains of the building blocks can be reduced. Its sensitivity to noise and nonlinearity of an individual building block can be reduced, but at the cost of that of other blocks; its sensitivity to noise and nonlinearity cannot be reduced over the whole system. Three design approaches are proposed, analyzed and compared. Statistical and corner simulations are performed to confirm the validity of the proposed guidelines showing significant improvement in the yield of the designs. Applying the analysis to a zero-IF three-stage 60 GHz receiver shows a significant improvement in the design yield, by nullifying the first order sensitivities of the overall performance to the individual gains of the blocks. Reduction of the second order sensitivity of the NPD to the gain of individual stages, by keeping the contribution factor of all the stages below one, results in further improvements in the design yield. The conventional optimum-power design methodology has been modified in a way that it nullifies the first order sensitivities of NPD to the individual gains of all the stages. It is shown that for simultaneous power optimization and reduced second-order sensitivity to the gains of the blocks less power hungry building blocks must be in the rear stages of the receiver and more power hungry ones in the front. After identifying the limitations of a pure system-level approach, i.e., inability to suppress the sensitivity of the overall performance to the noise and nonlinearity of all the blocks, the focus is shifted towards circuit-level methods by providing re-configurability to some RF circuits. A receiver is designed with good noise and nonlinearity performance and with accumulated noise and nonlinearity distortion contribution in its last stage (mixer). As a result, the overall performance of the receiver is more sensitive to the performance variations of the mixer. Simulations show that it is possible to correct the overall receiver performance degradations resulting from process variations by just tuning the performance of the mixer. Furthermore, a tunable mixer is presented for minimizing the IMD2 across a wide IF bandwidth. It is demonstrated both in theory and measurement that a presented three-dimensional tuning method is beneficial for wideband cancellation of second order intermodulation distortions (IMD2) in a zero-IF downconverter. A 60GHz zero-IF mixer is designed and measured on-wafer to show that the proposed tuning mechanism can simultaneously suppress IMD2 tones across the whole 1GHz IF band. To address the challenges of 60GHz circuit design, a design methodology is utilized which serves to properly model the parasitic effects and improve the predictability of the performance. The parasitic effects due to layout, which are more influential at high frequencies, are taken into account by performing automatic RC extraction and manual L extraction. The long signal lines are modeled with distributed RLC networks. The problem of substrate losses is addressed by using patterned ground shields in inductors and transmission lines. The cross-talk issue is treated by using distributed meshed ground lines, decoupled DC lines, and grounded substrate contacts around sensitive RF components. However, in practice, it is observed that accurate simulation of all the effects is sometimes very time consuming or even infeasible. For instance electromagnetic simulation of a transformer in the presence of all the dummy metals is beyond the computational capability of existing EM-simulators. Three 60GHz receiver components are analyzed, designed, and measured with good performance. A two-stage fully integrated 60 GHz differential low noise amplifier is implemented in a CMOS 65 nm bulk technology with superior noise figure compared to state-of-the-art mm-wave LNAs. A doublebalanced 60 GHz mixer with ac-coupled RF input is designed and measured with a series capacitor in the input RF path to suppress the low frequency second order intermodulation distortions generated in the previous stage. A quadrature 60 GHz VCO is presented which exhibits a comparable level of performance, in particular very good phase noise, to state-of-the-art single-phase VCOs, despite the additional challenges and limitations imposed by the quadrature topology. The on-wafer measurements on the 60GHz circuits designed in this work are performed using a waveguide-based measurement setup. The fixed waveguide structures, specially provided for the probe station, serve for the robustness of the setup as they circumvent the need for cables, which are by nature difficult to rigidify, in the vicinity of the probes. Taking advantage of magic- Ts, it is possible to measure differential mm-wave circuits with a two-port network analyzer rather than using a much more expensive four-port one. Noise, s-parameter, and phase noise measurements are performed using the mentioned setups

Design of reconfigurable multi-mode RF circuits

Wireless communication systems and devices have been developing at a much faster pace in the past few years. With the introduction of new applications and services and the increasing demand for higher data rate comes the need for new frequency bands and new standards. One critical issue for next generation wireless devices is how to support all of the existing and emerging bands while not increasing the cost and power consumption. A feasible solution is the concept of the software-defined radio where a single receiver can be reconfigured to operate in different modes, each of which supports one or several bands and/or standards. To implement such a reconfigurable receiver, reconfigurable RF building blocks, such as the LNA, mixer, VCO, etc., are required. This dissertation focuses on two key blocks: the low noise amplifier (LNA) and the voltage controlled oscillator (VCO). First the design, modeling and characterization of a multi-tap transformer are discussed. Simple mathematical calculations are utilized to estimate the inductances and coupling coefficients from the physical parameters of a multi-tap transformer. The design method is verified with several designed multi-tap transformers that are characterized up to 10 GHz using Momentum simulation results. The effect of switch loss on a switched multi-tap transformer is explored and a broadband lumped-element model of the multi-tap transformer is also proposed. Next a reconfigurable multimode LNA capable of single-band, concurrent dual-band, and ultra-wideband operation is presented. The multimode operation is realized by incorporating a switched multi-tap transformer into the input matching network of an inductively degenerated common source amplifier. The proposed LNA achieves single band matching at 2.8, 3.3, and 4.6 GHz; concurrent dual-band matching at 2.05 and 5.65 GHz; and ultra-wideband matching from 4.3 to 10.8 GHz. The chip was fabricated in a 0.13 m CMOS process, and occupies an area of 0.72 mm2, and has a power dissipation of 6.4 mW from a 1.2-V supply. Finally, a triple-mode VCO using a transformer-based 4th order tank with tunable transconductance cells coupling the primary and secondary inductor is introduced. The tank impedance can be re-shaped by the transconductance cells through the tuning of their biasing currents. With the control of biasing current, VCO is configured in three modes, capable of generating a single frequency in 3- and 5- GHz bands, respectively, and two frequencies in both 3- and 5- GHz bands simultaneously. The triple-mode VCO was fabricated in a 0.13 μm CMOS process, occupies an area of 0.16 mm2, and dissipates 5.6 mW from a 1.2-V supply

Integrated phased array systems in silicon

Silicon offers a new set of possibilities and challenges for RF, microwave, and millimeter-wave applications. While the high cutoff frequencies of the SiGe heterojunction bipolar transistors and the ever-shrinking feature sizes of MOSFETs hold a lot of promise, new design techniques need to be devised to deal with the realities of these technologies, such as low breakdown voltages, lossy substrates, low-Q passives, long interconnect parasitics, and high-frequency coupling issues. As an example of complete system integration in silicon, this paper presents the first fully integrated 24-GHz eight-element phased array receiver in 0.18-μm silicon-germanium and the first fully integrated 24-GHz four-element phased array transmitter with integrated power amplifiers in 0.18-μm CMOS. The transmitter and receiver are capable of beam forming and can be used for communication, ranging, positioning, and sensing applications