Comparative analysis of analog LDO design

The presented research analyses different topologies of low dropout (LDO) regulator, mostly focusing on different frequency compensation schemes and power supply rejection analysis. This thesis discusses different analog LDO topologies and analyzes how they achieve stability using small signal analysis and related equations. The power supply rejection (PSR) of a different error amplifier and pass device has been analyzed and concluded that a Type-B amplifier with n-channel metal oxide semiconductor field effect transistor (MOSFET) output stage or a Type-A amplifier with p channel MOSFET (PMOS) output stage yields the best PSR. Digital LDO regulator topologies have also been discussed. The digital LDO regulator is intriguing due to its low power and synthesizability, but it suffers from coarse voltage regulation and poor PSR compared to the analog LDO regulator

Power Management Circuits for Energy Harvesting Applications

Energy harvesting is the process of converting ambient available energy into usable electrical energy. Multiple types of sources are can be used to harness environmental energy: solar cells, kinetic transducers, thermal energy, and electromagnetic waves. This dissertation proposal focuses on the design of high efficiency, ultra-low power, power management units for DC energy harvesting sources. New architectures and design techniques are introduced to achieve high efficiency and performance while achieving maximum power extraction from the sources. The first part of the dissertation focuses on the application of inductive switching regulators and their use in energy harvesting applications. The second implements capacitive switching regulators to minimize the use of external components and present a minimal footprint solution for energy harvesting power management. Analysis and theoretical background for all switching regulators and linear regulators are described in detail. Both solutions demonstrate how low power, high efficiency design allows for a self-sustaining, operational device which can tackle the two main concerns for energy harvesting: maximum power extraction and voltage regulation. Furthermore, a practical demonstration with an Internet of Things type node is tested and positive results shown by a fully powered device from harvested energy. All systems were designed, implemented and tested to demonstrate proof-of-concept prototypes

Digital Intensive Mixed Signal Circuits with In-situ Performance Monitors

University of Minnesota Ph.D. dissertation.November 2016. Major: Electrical/Computer Engineering. Advisor: Chris Kim. 1 computer file (PDF); x, 137 pages.Digital intensive circuit design techniques of different mixed-signal systems such as data converters, clock generators, voltage regulators etc. are gaining attention for the implementation of modern microprocessors and system-on-chips (SoCs) in order to fully utilize the benefits of CMOS technology scaling. Moreover different performance improvement schemes, for example, noise reduction, spur cancellation, linearity improvement etc. can be easily performed in digital domain. In addition to that, increasing speed and complexity of modern SoCs necessitate the requirement of in-situ measurement schemes, primarily for high volume testing. In-situ measurements not only obviate the need for expensive measurement equipments and probing techniques, but also reduce the test time significantly when a large number of chips are required to be tested. Several digital intensive circuit design techniques are proposed in this dissertation along with different in-situ performance monitors for a variety of mixed signal systems. First, a novel beat frequency quantization technique is proposed in a two-step VCO quantizer based ADC implementation for direct digital conversion of low amplitude bio- potential signals. By direct conversion, it alleviates the requirement of the area and power consuming analog-frontend (AFE) used in a conventional ADC designs. This prototype design is realized in a 65nm CMOS technology. Measured SNDR is 44.5dB from a 10mVpp, 300Hz signal and power consumption is only 38μW. Next, three different clock generation circuits, a phase-locked loop (PLL), a multiplying delay-locked loop (MDLL) and a frequency-locked loop (FLL) are presented. First a 0.4-to-1.6GHz sub-sampling fractional-N all digital PLL architecture is discussed that utilizes a D-flip-flop as a digital sub-sampler. Measurement results from a 65nm CMOS test-chip shows 5dB lower phase noise at 100KHz offset frequency, compared to a conventional architecture. The Digital PLL (DPLL) architecture is further extended for a digital MDLL implementation in order to suppress the VCO phase noise beyond the DPLL bandwidth. A zero-offset aperture phase detector (APD) and a digital- to-time converter (DTC) are employed for static phase-offset (SPO) cancellation. A unique in-situ detection circuitry achieves a high resolution SPO measurement in time domain. A 65nm test-chip shows 0.2-to-1.45GHz output frequency range while reducing the phase-noise by 9dB compared to a DPLL. Next, a frequency-to-current converter (FTC) based fractional FLL is proposed for a low accuracy clock generation in an extremely low area for IoT application. High density deep-trench capacitors are used for area reduction. The test-chip is fabricated in a 32nm SOI technology that takes only 0.0054mm2 active area. A high-resolution in-situ period jitter measurement block is also incorporated in this design. Finally, a time based digital low dropout (DLDO) regulator architecture is proposed for fine grain power delivery over a wide load current dynamic range and input/output voltage in order to facilitate dynamic voltage and frequency scaling (DVFS). High- resolution beat frequency detector dynamically adjusts the loop sampling frequency for ripple and settling time reduction due to load transients. A fixed steady-state voltage offset provides inherent active voltage positioning (AVP) for ripple reduction. Circuit simulations in a 65nm technology show more than 90% current efficiency for 100X load current variation, while it can operate for an input voltage range of 0.6V – 1.2V

Energy Efficient Computing with Time-Based Digital Circuits

University of Minnesota Ph.D. dissertation. May 2019. Major: Electrical Engineering. Advisor: Chris Kim. 1 computer file (PDF); xv, 150 pages.Advancements in semiconductor technology have given the world economical, abundant, and reliable computing resources which have enabled countless breakthroughs in science, medicine, and agriculture which have improved the lives of many. Due to physics, the rate of these advancements is slowing, while the demand for the increasing computing horsepower ever grows. Novel computer architectures that leverage the foundation of conventional systems must become mainstream to continue providing the improved hardware required by engineers, scientists, and governments to innovate. This thesis provides a path forward by introducing multiple time-based computing architectures for a diverse range of applications. Simply put, time-based computing encodes the output of the computation in the time it takes to generate the result. Conventional systems encode this information in voltages across multiple signals; the performance of these systems is tightly coupled to improvements in semiconductor technology. Time-based computing elegantly uses the simplest of components from conventional systems to efficiently compute complex results. Two time-based neuromorphic computing platforms, based on a ring oscillator and a digital delay line, are described. An analog-to-digital converter is designed in the time domain using a beat frequency circuit which is used to record brain activity. A novel path planning architecture, with designs for 2D and 3D routes, is implemented in the time domain. Finally, a machine learning application using time domain inputs enables improved performance of heart rate prediction, biometric identification, and introduces a new method for using machine learning to predict temporal signal sequences. As these innovative architectures are presented, it will become clear the way forward will be increasingly enabled with time-based designs

Interfaces neuronales CMOS haute résolution pour l'électrophysiologie et l'optogénétique en boucle fermée

L’avenir de la recherche sur les maladies du cerveau repose sur le développement de nouvelles technologies qui permettront de comprendre comment cet organe si complexe traite, intègre et transfère l’information. Parmi celles-ci, l’optogénétique est une technologie révolutionnaire qui permet d’utiliser de la lumière afin d’activer sélectivement les neurones du cortex d’animaux transgéniques pour observer leur effet dans un vaste réseau biologique. Ce cadre expérimental repose typiquement sur l’observation de l’activité neuronale de souris transgéniques, car elles peuvent exprimer une grande variété de gènes et de maladies et qu’elles sont peu couteuses. Toutefois, la plupart des appareils de mesure ou de stimulation optogénétique disponible ne sont pas appropriés, car ils sont câblés, trop lourds et/ou trop simplistes. Malheureusement, peu de systèmes sans fil existent, et ces derniers sont grandement limités par la bande passante requise pour transmettre les données neuronales, et ils ne fournissent pas de stimulation optogénétique multicanal afin de stimuler et observer plusieurs régions du cerveau. Dans les dispositifs actuels, l’interprétation des données neuronales est effectuée ex situ, alors que la recherche bénéficierait grandement de systèmes sans fil assez intelligents pour interpréter et stimuler les neurones en boucle fermée, in situ. Le but de ce projet de recherche est de concevoir des circuits analogiques-numériques d’acquisition et de traitement des signaux neuronaux, des algorithmes d’analyse et de traitement de ces signaux et des systèmes electro-optiques miniatures et sans fil pour : i) Mener des expériences combinant l’enregistrement neuronal et l’optogénétique multicanal haute résolution avec des animaux libres de leurs mouvements. ii) Mener des expériences optogénétiques synchronisées avec l’observation, c.-à-d. en boucle fermée, chez des animaux libres de leurs mouvements. iii) Réduire la taille, le poids et la consommation énergétique des systèmes optogénétiques sans fil afin de minimiser l’impact de la recherche chez de petits animaux. Ce projet est en 3 phases, et ses principales contributions ont été rapportées dans dix conférences internationales (ISSCC, ISCAS, EMBC, etc.) et quatre articles de journaux publiés ou soumis, ainsi que dans un brevet et deux divulgations. La conception d’un système optogénétique haute résolution pose plusieurs défis importants. Notamment, puisque les signaux neuronaux ont un contenu fréquentiel élevé (_10 kHz), le nombre de canaux sous observation est limité par la bande passante des transmetteurs sans fil (2-4 canaux en général). Ainsi, la première phase du projet a visé le développement d’algorithmes de compression des signaux neuronaux et leur intégration dans un système optogénétique sans fil miniature et léger (2.8 g) haute résolution possédant 32 canaux d’acquisition et 32 canaux de stimulation optique. Le système détecte, compresse et transmet les formes d’onde des potentiels d’action (PA) produits par les neurones avec un field programmable gate array (FPGA) embarqué à faible consommation énergétique. Ce processeur implémente un algorithme de détection des PAs basé sur un seuillage adaptatif, ce qui permet de compresser les signaux en transmettant seulement les formes détectées. Chaque PA est davantage compressé par une transformée en ondelette discrète (DWT) de type Symmlet-2 suivie d’une technique de discrimination et de requantification dynamique des coefficients. Les résultats obtenus démontrent que cet algorithme est plus robuste que les méthodes existantes tout en permettant de reconstruire les signaux compressés avec une meilleure qualité (SNDR moyen de 25 dB _ 5% pour un taux de compression (CR) de 4.2). Avec la détection, des CR supérieurs à 500 sont rapportés lors de la validation in vivo. L’utilisation de composantes commerciales dans des systèmes optogénétiques sans fil augmentela taille et la consommation énergétique, en plus de ne pas être optimisée pour cette application. La seconde phase du projet a permis de concevoir un système sur puce (SoC) complementary metal oxide semiconductor (CMOS) pour faire de l’enregistrement neuronal et de optogénétique multicanal, permettant de réduire significativement la taille et la consommation énergétique comparativement aux alternatives commerciales. Ceci est une contribution importante, car c’est la première puce à être doté de ces deux fonctionnalités. Le SoC possède 10 canaux d’enregistrement et 4 canaux de stimulation optogénétique. La conception du bioamplificateur inclut une bande passante programmable (0.5 Hz - 7 kHz) et un faible bruit referré à l’entré (IRN de 3.2 μVrms), ce qui permet de cibler différents types de signaux biologiques (PA, LFP, etc.). Le convertisseur analogique numérique (ADC) de type Delta- Sigma (DS) MASH 1-1-1 est conçu pour fonctionner de faibles taux de sur-échantillonnage (OSR _50) pour réduire sa consommation et possède une résolution programmable (ENOB de 9.75 Bits avec un OSR de 25). Cet ADC exploite une nouvelle technique réduisant la taille du circuit en soustrayant la sortie de chaque branche du DS dans le domaine numérique, comparativement à la méthode analogique classique. La consommation totale d’un canal d’enregistrement est de 11.2 μW. Le SoC implémente un nouveau circuit de stimulation optique basé sur une source de courant de type cascode avec rétroaction, ce qui permet d’accommoder une large gamme de LED et de tensions de batterie comparativement aux circuits existants. Le SoC est intégré dans un système optogénétique sans fil et validé in vivo. À ce jour et en excluant ce projet, aucun système sans-fil ne fait de l’optogénétique en boucle fermée simultanément au suivi temps réel de l’activité neuronale. Une contribution importante de ce travail est d’avoir développé le premier système optogénétique multicanal qui est capable de fonctionner en boucle fermée et le premier à être validé lors d’expériences in vivo impliquant des animaux libres de leurs mouvements. Pour ce faire, la troisième phase du projet a visé la conception d’un SoC CMOS numérique, appelé neural decoder integrated circuit (ND-IC). Le ND-IC et le SoC développé lors de la phase 2 ont été intégrés dans un système optogénétique sans fil. Le ND-IC possède 3 modules : 1) le détecteur de PA adaptatif, 2) le module de compression possédant un nouvel arbre de tri pour discriminer les coefficients, et 3) le module de classement automatique des PA qui réutilise les données générées par le module de détection et de compression pour réduire sa complexité. Un lien entre un canal d’enregistrement et un canal de stimulation est établi selon l’association de chaque PA à un neurone, grâce à la classification, et selon l’activité de ce neurone dans le temps. Le ND-IC consomme 56.9 μW et occupe 0.08 mm2 par canal. Le système pèse 1.05 g, occupe un volume de 1.12 cm3, possède une autonomie de 3h, et est validé in vivo.The future of brain research lies in the development of new technologies that will help understand how this complex organ processes, integrates and transfers information. Among these, optogenetics is a recent technology that allows the use of light to selectively activate neurons in the cortex of transgenic animals to observe their effect in a large biological network. This experimental setting is typically based on observing the neuronal activity of transgenic mice, as they express a wide variety of genes and diseases, while being inexpensive. However, most available neural recording or optogenetic devices are not suitable, because they are hard-wired, too heavy and/or too simplistic. Unfortunately, few wireless systems exist, and they are greatly limited by the required bandwidth to transmit neural data, while not providing simultaneous multi-channel neural recording and optogenetic, a must for stimulating and observing several areas of the brain. In current devices, the analysis of the neuronal data is performed ex situ, while the research would greatly benefit from wireless systems that are smart enough to interpret and stimulate the neurons in closed-loop, in situ. The goal of this project is to design analog-digital circuits for acquisition and processing of neural signals, algorithms for analysis and processing of these signals and miniature electrooptical wireless systems for: i) Conducting experiments combining high-resolution multi-channel neuronal recording and high-resolution multi-channel optogenetics with freely-moving animals. ii) Conduct optogenetic experiments synchronized with the neural recording, i.e. in closed loop, with freely-moving animals. iii) Increase the resolution while reducing the size, weight and energy consumption of the wireless optogenetic systems to minimize the impact of research with small animals. This project is in 3 phases, and its main contributions have been reported in ten conferences (ISSCC, ISCAS, EMBC, etc.) and four published journal papers, or submitted, as well as in a patent and two disclosures. The design of a high resolution optogenetic system poses several challenges. In particular, since the neuronal signals have a high frequency content (10 kHz), the number of chanv nels under observation is limited by the bandwidth of the wireless transmitters (2-4 channels in general). Thus, the first phase of the project focused on the development of neural signal compression algorithms and their integration into a high-resolution miniature and lightweight wireless optogenetics system (2.8g), having 32 recording channels and 32 optical stimulation channels. This system detects, compresses and transmits the waveforms of the signals produced by the neurons, i.e. action potentials (AP), in real time, via an embedded low-power field programmable gate array (FPGA). This processor implements an AP detector algorithm based on adaptive thresholding, which allows to compress the signals by transmitting only the detected waveforms. Each AP is further compressed by a Symmlet-2 discrete wavelet transform (DWT) followed dynamic discrimination and requantification of the DWT coefficients, making it possible to achieve high compression ratios with a good reconstruction quality. Results demonstrate that this algorithm is more robust than existing approach, while allowing to reconstruct the compressed signals with better quality (average SNDR of 25 dB 5% for a compression ratio (CR) of 4.2). With detection, CRs greater than 500 are reported during the in vivo validation. The use of commercial components in wireless optogenetic systems increases the size and power consumption, while not being optimized for this application. The second phase of the project consisted in designing a complementary metal oxide semiconductor (CMOS) system-on-chip (SoC) for neural recording and multi-channel optogenetics, which significantly reduces the size and energy consumption compared to commercial alternatives. This is important contribution, since it’s the first chip to integrate both features. This SoC has 10 recording channels and 4 optogenetic stimulation channels. The bioamplifier design includes a programmable bandwidth (0.5 Hz -7 kHz) and a low input-referred noise (IRN of 3.2 μVrms), which allows targeting different biological signals (AP, LFP, etc.). The Delta-Sigma (DS) MASH 1-1-1 low-power analog-to-digital converter (ADC) is designed to work with low OSR (50), as to reduce its power consumption, and has a programmable resolution (ENOB of 9.75 bits with an OSR of 25). This ADC uses a new technique to reduce its circuit size by subtracting the output of each DS branch in the digital domain, rather than in the analog domain, as done conventionally. A recording channel, including the bioamplifier, the DS and the decimation filter, consumes 11.2 μW. Optical stimulation is performed with an on-chip LED driver using a regulated cascode current source with feedback, which accommodates a wide range of LED parameters and battery voltages. The SoC is integrated into a wireless optogenetic platform and validated in vivo.To date and excluding this project, no wireless system is making closed-loop optogenetics simultaneously to real-time monitoring of neuronal activity. An important contribution of this work is to have developed the first multi-channel optogenetic system that is able to work in closed-loop, and the first to be validated during in vivo experiments involving freely-moving animals. To do so, the third phase of the project aimed to design a digital CMOS chip, called neural decoder integrated circuit (ND-IC). The ND-IC and the SoC developed in Phase 2 are integrated within a wireless optogenetic system. The ND-IC has 3 main cores: 1) the adaptive AP detector core, 2) the compression core with a new sorting tree for discriminating the DWT coefficients, and 3 ) the AP automatic classification core that reuses the data generated by the detection and compression cores to reduce its complexity. A link between a recording channel and a stimulation channel is established according to the association of each AP with a neuron, thanks to the classification, and according to the bursting activity of this neuron. The ND-IC consumes 56.9 μW and occupies 0.08 mm2 per channel. The system weighs 1.05 g, occupies a volume of 1.12 cm3, has an autonomy of 3h, and is validated in vivo

비디오 클럭 주파수 보상 구조를 이용한 디스플레이포트 수신단 설계

학위논문 (박사)-- 서울대학교 대학원 : 전기·컴퓨터공학부, 2014. 8. 정덕균.This thesis presents the design of DisplayPort receiver which is a high speed digital display interface replacing existing interfaces such as DVI, HDMI, LVDS and so on. The two prototype chips are fabricated, one is a 5.4/2.7/1.62-Gb/s multi-rate DisplayPort receiver and the other is a 2.7/1.62-Gb/s multi-rate Embedded DisplayPort (eDP) receiver for an intra-panel display interface. The first receiver which is designed to support the external box-to-box display connection provides up to 4K resolution (4096×2160) with the maximum data rate of 21.6 Gb/s when 4 lanes are all used. The second one aims to connect internal chip-to-chip connection such as graphic processors to display panels in notebooks or tablet PCs. It supports the maximum data rate of 10.8 Gb/s with 4-lane operation which is able to provide the resolution of WQXGA (2560×1600). Since there is no dedicated clock channel, it must contain clock and data recovery (CDR) circuit to extract the link clock from the data stream. All-Digital CDR (ADCDR) is adopted for area efficiency and better performances of the multi-rate operation. The link rate is fixed but the video clock frequency range is fairly wide for supporting all display resolutions and frame rates. Thus, the wide range video clock frequency synthesizer is essential for reconstructing the transmitted video data. A source device starts link training before transmitting video data to recover the clock and establish the link. When the loss of synchronization between the source device and the sink device happens, it usually restarts the link training and try to re-establish the link. Since link training spends several milliseconds for initializing, the video image is not displayed properly in the sink device during this interval. The proposed clock recovery scheme can significantly shorten the time to recover from the link failure with the ADCDR topology. Once the link is established after link training, the ADCDR memorizes the DCO codes of the synchronization state and when the loss of synchronization happens, it restores the previous DCO code so that the clock is quickly recovered from the failure state without the link re-training. The direct all-digital frequency synthesizer is proposed to generate the cycle-accurate video clock frequency. The video clock frequency has wide range to cover all display formats and is determined by the division ratio of large M and N values. The proposed frequency synthesizer using a programmable integer divider and a multi-phase switching fractional divider with the delta-sigma modulation exhibits better performances and reduces the design complexity operating with the existing clock from the ADCDR circuit. In asynchronous clock system, the transmitted M value which changes over time is measured by using a counter running with the long reference period (N cycles) and updated once per blank period. Thus, the transmitted M is not accurate due to its low update rate, transport latency and quantization error. The proposed frequency error compensation scheme resolves these problems by monitoring the status of FIFO between the clock domains. The first prototype chip is fabricated in a 65-nm CMOS process and the physical layer occupies 1.39 mm2 and the estimated area of the link layer is 2.26 mm2. The physical layer dissipates 86/101/116 mW at 1.62/2.7/5.4 Gb/s data rate with all 4-lane operation. The power consumption of the link layer is 107/145/167 mW at 1.62/2.7/5.4 Gb/s. The second prototype chip, fabricated in a 0.13μm CMOS process, presents the physical layer area of 1.59 mm2 and the link layer area of 3.01 mm2. The physical layer dissipates 21 mW at 1.62 Gb/s and 29 mW at 2.7 Gb/s with 2-lane operation. The power consumption of the link layer is 31 mW at 1.62 Gb/s and 41 mW at 2.7 Gb/s with 2-lane operation. The core area of the video clock synthesizer occupies 0.04 mm2 and the power dissipation is 5.5 mW at a low bit rate and 9.1 mW at a high bit rate. The output frequency range is 25 to 330 MHz.ABSTRACT I CONTENTS IV LIST OF FIGURES VII LIST OF TABLES XII CHAPTER 1 INTRODUCTION 1 1.1 BACKGROUND 1 1.2 MOTIVATION 4 1.3 THESIS ORGANIZATION 12 CHAPTER 2 DIGITAL DISPLAY INTERFACE 13 2.1 OVERVIEW 13 2.2 DISPLAYPORT INTERFACE CHARACTERISTICS 18 2.2.1 DISPLAYPORT VERSION 1.2 18 2.2.2 EMBEDDED DISPLAYPORT VERSION 1.2 21 2.3 DISPLAYPORT INTERFACE ARCHITECTURE 23 2.3.1 LAYERED ARCHITECTURE 23 2.3.2 MAIN STREAM PROTOCOL 27 2.3.3 INITIALIZATION AND LINK TRAINING 30 2.3.3 VIDEO STREAM CLOCK RECOVERY 35 CHAPTER 3 DESIGN OF DISPLAYPORT RECEIVER 39 3.1 OVERVIEW 39 3.2 PHYSICAL LAYER 43 3.3 LINK LAYER 55 3.3.1 OVERALL ARCHITECTURE 55 3.3.2 AUX CHANNEL 58 3.3.3 VIDEO TIMING GENERATION 61 3.3.4 CONTENT PROTECTION 63 3.3.5 AUDIO TRANSMISSION 66 3.4 EXPERIMENTAL RESULTS 68 CHAPTER 4 DESIGN OF EMBEDDED DISPLAYPORT RECEIVER 81 4.1 OVERVIEW 81 4.2 PHYSICAL LAYER 84 4.3 LINK LAYER 88 4.3.1 OVERALL ARCHITECTURE 88 4.3.2 MAIN LINK STREAM 90 4.3.3 CONTENT PROTECTION 93 4.4 PROPOSED CLOCK RECOVERY SCHEME 94 4.5 EXPERIMENTAL RESULTS 100 CHAPTER 5 PROPOSED VIDEO CLOCK SYNTHESIZER AND FREQUENCY CONTROL SCHEME 113 5.1 MOTIVATION 113 5.2 PROPOSED VIDEO CLOCK SYNTHESIZER 115 5.3 BUILDING BLOCKS 121 5.4 FREQUENCY ERROR COMPENSATION 126 5.5 EXPERIMENTAL RESULTS 131 CHAPTER 6 CONCLUSION 138 BIBLIOGRAPHY 141 초 록 152Docto

MEMS piezoelectric vibrational energy harvesters and circuits for IoT applications

In the Internet of Things (IoT) world, more and more sensor nodes are being deployed and more mobile power sources are required. Alternative solutions to batteries are the subjects of worldwide extended research. Among the possibilities is the harvesting of energy from the ambient. A novel energy harvesting system to power wireless sensor nodes is a necessity and inevitable path, with more and more market interest. Microelectromechnaical systems (MEMS) based piezoelectric vibrational energy harvesters (PVEH) are considered in this thesis due to their good energy densities, conversion efficiency, suitability for miniaturization and CMOS integration. Cantilever beams are favored for their relatively high average strains, low frequencies and simplicity of fabrication. Proof masses are essential in micro scale devices in order to decrease the resonance frequency and increase the strain along the beam to increase the output power. In this thesis, the effects of proof mass geometry on piezoelectric vibration energy harvesters are studied. Different geometrical dimension ratios have significant impact on the resonance frequency, e.g., beam to mass lengths, and beam to mass widths. The responses of various prototypes are studied. Furthermore, the impact of geometry on the performance of cantilever-based PVEH is investigated. Namely, rectangular and trapezoidal T-shaped designs are fabricated and tested. Optimized cross-shaped geometries are fabricated using a commercial technology PiezoMUMPs process from MEMSCAP. They are characterized for their resonant frequency, strain distribution and output power. The output of an energy harvester is not directly suited as a power supply for circuits because of variations in its power and voltage over time, therefore a power management circuit is required. The circuit meets the requirements of responding to an input voltage that varies with the ambient conditions to generate a regulated output voltage, and the ability to power multiple outputs from a fixed input voltage. In this thesis, new design architectures for a reconfigurable circuit are considered. A charge pump which modifies dynamically the number of stages to generate a plurality of voltage levels has been designed and fabricated using a CMOS 0.13 μm technology. This provides biasing voltages for electrostatic MEMS devices. Electrostatic MEMS require relatively high and variable actuation voltages and the fabricated circuit serves this goal and attains a measured maximum output voltage of 10.1 V from a 1.2 V supply. In this thesis, design recommendations are given and MEMS piezoelectric harvesters are implemented and validated through fabrications. T-shaped harvesters bring improvements over cantilever designs, namely the trapezoidal T-shaped structures. A cross-shaped design has the advantage of utilizing four beams and the proposed proof mass improves the performance significantly. A cross-coupled circuit rectifies the output efficiently towards an optimal energy harvesting solution

Topical Workshop on Electronics for Particle Physics

The purpose of the workshop was to present results and original concepts for electronics research and development relevant to particle physics experiments as well as accelerator and beam instrumentation at future facilities; to review the status of electronics for the LHC experiments; to identify and encourage common efforts for the development of electronics; and to promote information exchange and collaboration in the relevant engineering and physics communities