3,399 research outputs found
Enhanced Sensitivity of CMOS Image Sensors by Stacked Diodes
We have investigated and compared the performance of photodiodes built with stacked p/n junctions operating in parallel versus conventional ones made with single p/n junctions. We propose a method to characterize and compare photodiodes sensitivity. For this purpose, a dedicated chip in the standard AMS 180-nm HV technology has been fabricated. Four different sensor structures were implemented and compared. Experimental results are provided. Measurements show sensitivity enhancement ranging from 55% to 70% within the 500-1100 nm spectral region. The larger increment is happening in the near infrared band (up to 62%). Such results make stacked photodiodes suitable candidates for the implementation of photosensors in vision chips designed for standard CMOS technologies.Ministerio de Economía y Competitividad TEC2012-33634, TEC2015-66878- C3-1-RJunta de Andalucía TIC 2012-2338Office of Naval Research (USA) N00014141035
Advances on CMOS image sensors
This paper offers an introduction to the technological advances of image sensors designed using
complementary metal–oxide–semiconductor (CMOS) processes along the last decades. We review
some of those technological advances and examine potential disruptive growth directions for CMOS
image sensors and proposed ways to achieve them. Those advances include breakthroughs on
image quality such as resolution, capture speed, light sensitivity and color detection and advances on
the computational imaging. The current trend is to push the innovation efforts even further as the
market requires higher resolution, higher speed, lower power consumption and, mainly, lower cost
sensors. Although CMOS image sensors are currently used in several different applications from
consumer to defense to medical diagnosis, product differentiation is becoming both a requirement and
a difficult goal for any image sensor manufacturer. The unique properties of CMOS process allows the
integration of several signal processing techniques and are driving the impressive advancement of the
computational imaging. With this paper, we offer a very comprehensive review of methods,
techniques, designs and fabrication of CMOS image sensors that have impacted or might will impact
the images sensor applications and markets
Extending systems-on-chip to the third dimension : performance, cost and technological tradeoffs.
Because of the today's market demand for high-performance, high-density portable hand-held applications, electronic system design technology has shifted the focus from 2-D planar SoC single-chip solutions to different alternative options as tiled silicon and single-level embedded modules as well as 3-D integration. Among the various choices, finding an optimal solution for system implementation dealt usually with cost, performance and other technological trade-off analysis at the system conceptual level. It has been identified that the decisions made within the first 20% of the total design cycle time will ultimately result up to 80% of the final product cost. In this paper, we discuss appropriate and realistic metric for performance and cost trade-off analysis both at system conceptual level (up-front in the design phase) and at implementation phase for verification in the three-dimensional integration. In order to validate the methodology, two ubiquitous electronic systems are analyzed under various implementation schemes and discuss the pros and cons of each of them
Offset-compensated comparator with full-input range in 150nm FDSOI CMOS-3d technology
This paper addresses an offset-compensated comparator
with full-input range in the 150nm FDSOI CMOS-
3D technology from MIT- Lincoln Laboratory. The comparator
discussed here makes part of a vision system. Its architecture is
that of a self-biased inverter with dynamic offset correction. At
simulation level, the comparator can reach a resolution of 0.1mV
in an area of approximately 220μm2 with a time response of less
than 40ns and a static power dissipation of 1.125μW
Technologies for 3D Heterogeneous Integration
3D-Integration is a promising technology towards higher interconnect
densities and shorter wiring lengths between multiple chip stacks, thus
achieving a very high performance level combined with low power consumption.
This technology also offers the possibility to build up systems with high
complexity just by combining devices of different technologies. For ultra thin
silicon is the base of this integration technology, the fundamental processing
steps will be described, as well as appropriate handling concepts. Three main
concepts for 3D integration have been developed at IZM. The approach with the
greatest flexibility called Inter Chip Via - Solid Liquid Interdiffusion
(ICV-SLID) is introduced. This is a chip-to-wafer stacking technology which
combines the advantages of the Inter Chip Via (ICV) process and the
solid-liquid-interdiffusion technique (SLID) of copper and tin. The fully
modular ICV-SLID concept allows the formation of multiple device stacks. A test
chip was designed and the total process sequence of the ICV-SLID technology for
the realization of a three-layer chip-to-wafer stack was demonstrated. The
proposed wafer-level 3D integration concept has the potential for low cost
fabrication of multi-layer high-performance 3D-SoCs and is well suited as a
replacement for embedded technologies based on monolithic integration. To
address yield issues a wafer-level chip-scale handling is presented as well, to
select known-good dies and work on them with wafer-level process sequences
before joining them to integrated stacks.Comment: Submitted on behalf of EDA Publishing Association
(http://irevues.inist.fr/handle/2042/16838
On evolution of CMOS image sensors
CMOS Image Sensors have become the principal technology in majority of digital cameras. They started replacing the film and Charge Coupled Devices in the last decade with the promise of lower cost, lower power requirement, higher integration and the potential of focal plane processing. However, the principal factor behind their success has been the ability to utilise the shrinkage in CMOS technology to make smaller pixels, and thereby have more resolution without increasing the cost. With the market of image sensors exploding courtesy their inte- gration with communication and computation devices, technology developers improved the CMOS processes to have better optical performance. Nevertheless, the promises of focal plane processing as well as on-chip integration have not been fulfilled. The market is still being pushed by the desire of having higher number of pixels and better image quality, however, differentiation is being difficult for any image sensor manufacturer. In the paper, we will explore potential disruptive growth directions for CMOS Image sensors and ways to achieve the same
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