A VCO-based CMOS readout circuit for capacitive MEMS microphones

Microelectromechanical systems (MEMS) microphone sensors have significantly improved in the past years, while the readout electronic is mainly implemented using switched-capacitor technology. The development of new battery powered 'always-on” applications increasingly requires a low power consumption. In this paper, we show a new readout circuit approach which is based on a mostly digital Sigma Delta (SigmaDelta) analog-to-digital converter (ADC). The operating principle of the readout circuit consists of coupling the MEMS sensor to an impedance converter that modulates the frequency of a stacked-ring oscillator—a new voltage-controlled oscillator (VCO) circuit featuring a good trade-off between phase noise and power consumption. The frequency coded signal is then sampled and converted into a noise-shaped digital sequence by a time-to-digital converter (TDC). A time-efficient design methodology has been used to optimize the sensitivity of the oscillator combined with the phase noise induced by 1/𝑓 and thermal noise. The circuit has been prototyped in a 130 nm CMOS process and directly bonded to a standard MEMS microphone. The proposed VCO-based analog-to-digital converter (VCO-ADC) has been characterized electrically and acoustically. The peak signal-to-noise and distortion ratio (SNDR) obtained from measurements is 77.9 dB-A and the dynamic range (DR) is 100 dB-A. The current consumption is 750 muA at 1.8 V and the effective area is 0.12 mm2. This new readout circuit may represent an enabling advance for low-cost digital MEMS microphones.This research was funded by project TEC2017-82653-R of CICYT, Spain

A 0.3 V rail-to-rail ultra-low-power OTA with improved bandwidth and slew rate

In this paper, we present a novel operational transconductance amplifier (OTA) topology based on a dual-path body-driven input stage that exploits a body-driven current mirror-active load and targets ultra-low-power (ULP) and ultra-low-voltage (ULV) applications, such as IoT or biomedical devices. The proposed OTA exhibits only one high-impedance node, and can therefore be compensated at the output stage, thus not requiring Miller compensation. The input stage ensures rail-to-rail input common-mode range, whereas the gate-driven output stage ensures both a high open-loop gain and an enhanced slew rate. The proposed amplifier was designed in an STMicroelectronics 130 nm CMOS process with a nominal supply voltage of only 0.3 V, and it achieved very good values for both the small-signal and large-signal Figures of Merit. Extensive PVT (process, supply voltage, and temperature) and mismatch simulations are reported to prove the robustness of the proposed amplifier

Encryption AXI Transaction Core for Enhanced FPGA Security

The current hot topic in cyber-security is not constrained to software layers. As attacks on electronic circuits have become more usual and dangerous, hardening digital System-on-Chips has become crucial. This article presents a novel electronic core to encrypt and decrypt data between two digital modules through an Advanced eXtensible Interface (AXI) connection. The core is compatible with AXI and is based on a Trivium stream cipher. Its implementation has been tested on a Zynq platform. The core prevents unauthorized data extraction by encrypting data on the fly. In addition, it takes up a small area—242 LUTs—and, as the core’s AXI to AXI path is fully combinational, it does not interfere with the system’s overall performance, with a maximum AXI clock frequency of 175 MHz.This work has been supported within the fund for research groups of the Basque university system IT1440-22 by the Department of Education and within the PILAR ZE-2020/00022 and COMMUTE ZE-2021/00931 projects by the Hazitek program, both of the Basque Government, the latter also by the Ministerio de Ciencia e Innovación of Spain through the Centro para el Desarrollo Tecnológico Industrial (CDTI) within the project IDI-20201264 and IDI-20220543 and through the Fondo Europeo de Desarrollo Regional 2014–2020 (FEDER funds)

A rectifier circuit using add-differentiate IC with a minimal number of CMOS transistors

Minayi, Elham (Dogus Author) -- Conference full title: 25th IEEE International Conference on Electronics Circuits and Systems, ICECS 2018; Bordeaux; France; 9 December 2018 through 12 December 2018.Using the recently developed Add-Differentiate 5-terminal Integrated Circuit, AD-IC (which possess 12 CMOS transistors only), augmented with two diodes, a new rectifier configuration is presented. Transistor level circuit and its layout are provided and the rectifier is simulated with parameters extracted from the layout showing very good conformity with desired rectifier behavior. Finally, a table of comparison of the proposed rectifier with fourteen others, existing in the literature, is included to conclude the paper

Skyrmion Logic-In-Memory Architecture for Maximum/Minimum Search

In modern computing systems there is the need to utilize a large amount of data in maintaining high efficiency. Limited memory bandwidth, coupled with the performance gap between memory and logic, impacts heavily on algorithms performance, increasing the overall time and energy required for computation. A possible approach to overcome such limitations is Logic-In-Memory (LIM). In this paper, we propose a LIM architecture based on a non-volatile skyrmion-based recetrack memory. The architecture can be used as a memory or can perform advanced logic functions on the stored data, for example searching for the maximum/minimum number. The circuit has been designed and validated using physical simulations for the memory array together with digital design tools for the control logic. The results highlight the small area of the proposed architecture and its good energy efficiency compared with a reference CMOS implementation

RISC-Vlim, a RISC-V Framework for Logic-in-Memory Architectures

Most modern CPU architectures are based on the von Neumann principle, where memory and processing units are separate entities. Although processing unit performance has improved over the years, memory capacity has not followed the same trend, creating a performance gap between them. This problem is known as the "memory wall" and severely limits the performance of a microprocessor. One of the most promising solutions is the "logic-in-memory" approach. It consists of merging memory and logic units, enabling data to be processed directly inside the memory itself. Here we propose an RISC-V framework that supports logic-in-memory operations. We substitute data memory with a circuit capable of storing data and of performing in-memory computation. The framework is based on a standard memory interface, so different logic-in-memory architectures can be inserted inside the microprocessor, based both on CMOS and emerging technologies. The main advantage of this framework is the possibility of comparing the performance of different logic-in-memory solutions on code execution. We demonstrate the effectiveness of the framework using a CMOS volatile memory and a memory based on a new emerging technology, racetrack logic. The results demonstrate an improvement in algorithm execution speed and a reduction in energy consumption

Selective Noise Based Power-Efficient and Effective Countermeasure against Thermal Covert Channel Attacks in Multi-Core Systems

With increasing interest in multi-core systems, such as any communication systems, infra-structures can become targets for information leakages via covert channel communication. Covert channel attacks lead to leaking secret information and data. To design countermeasures against these threats, we need to have good knowledge about classes of covert channel attacks along with their properties. Temperature–based covert communication channel, known as Thermal Covert Channel (TCC), can pose a threat to the security of critical information and data. In this paper, we present a novel scheme against such TCC attacks. The scheme adds selective noise to the thermal signal so that any possible TCC attack can be wiped out. The noise addition only happens at instances when there are chances of correct information exchange to increase the bit error rate (BER) and keep the power consumption low. Our experiments have illustrated that the BER of a TCC attack can increase to 94% while having similar power consumption as that of state-of-the-art

StaTI: Protecting against Fault Attacks Using Stable Threshold Implementations

Fault attacks impose a serious threat against the practical implementations of cryptographic algorithms. Statistical Ineffective Fault Attacks (SIFA), exploiting the dependency between the secret data and the fault propagation overcame many of the known countermeasures. Later, several countermeasures have been proposed to tackle this attack using error detection methods. However, the efficiency of the countermeasures, in part governed by the number of error checks, still remains a challenge. In this work, we propose a fault countermeasure, StaTI, based on threshold implementations and linear encoding techniques. The proposed countermeasure protects the implementations of cryptographic algorithms against both side-channel and fault adversaries in a non-combined attack setting. We present a new composable notion, stability, to protect a threshold implementation against a formal gate/register-faulting adversary. Stability ensures fault propagation, making a single error check of the output suffice. To illustrate the stability notion, first, we provide stable encodings of the XOR and AND gates. Then, we present techniques to encode threshold implementations of S-boxes, and provide stable encodings of some quadratic S-boxes together with their security and performance evaluation. Additionally, we propose general encoding techniques to transform a threshold implementation of any function (e.g., non-injective functions) to a stable one. We then provide an encoding technique to use in symmetric primitives which encodes state elements together significantly reducing the encoded state size. Finally, we used StaTI to implement a secure Keccak on FPGA and report on its efficiency

Application of memristors in realization of microwave passive circuits

Предмет истраживања ове докторске дисертације је примјена мемристора у реализацији планарних микроталасних пасивних кола. У фокусу истраживања је микроталасни помјерач фазе остварен коришћењем мемристивних прекидача. Истраживање обухвата и реализацију микроталасних филтара са мемристорима. Циљ истраживања је реализација микроталасног помјерача фазе који има боље карактеристике у односу на карактеристике одговарајућих помјерача фазе објављених у доступној отвореној литератури, а који користе традиционалне прекидаче као што су PIN диоде, микроелектромеханички прекидачи и CMOS. Такође, циљ истраживања представља и анализа могућих реализација микроталасних филтара коришћењем мемристора. Доприноси дисертације су нов метод пројектовања помјерача фазе, коришћењем мемристора, а којим се смањује потрошња уређаја и поправља константност фазног помјераја у специфицираном фреквенцијском опсегу. При реализацији филтара, коришћењем мемристора потиснути су нежељени пропусни опсези, реализован је реконфигурабилни филтар коришћењем мемристивних прекидача. Поред тога, пројектован је хардвер за аутоматско програмирање комерцијално доступног мемристора компаније KnowM, развијен је алгоритам и софтвер микроконтролера који омогућава аутоматско програмирање, као и софтвер преносивог или удаљеног уређаја за контролу рада микроконтролера. Пројектована су електрична кола остварена коришћењем комерцијално доступног мемристора. Предложен је модел за фреквенцијску анализу комерцијално доступног мемристора на учестаностима до 1 MHz. Пројектован је активни филтар пропусник опсега, који има могућност подешавања централне фреквенције при радном режиму. За експерименталну верификацију рада програматора и електричних кола направљени су лабораторијски прототипови.The scope of the research presented in this doctoral dissertation is the application of memristors in the realization of planar microwave passive circuits. The focus of the research was the microwave phase shifter realized using memristive switches. In addition, the research includes the realization of microwave filters by incorporating memristors. The aim of the research is the realization of a microwave phase shifter with better characteristics compared to the characteristics of phase shifters available in the open literature, which use traditional switches like PIN diodes, microelectromechanical systems, and CMOS. Also, the aim of the research is the analysis of microwave filters with incorporated memristors. The contribution of the doctoral dissertation is a novel method of designing microwave phase shifters - by using memristors which reduces the power consumption of the device and improves the constancy of the phase shift in the specified frequency range. By using memristors in the realization of filters, unwanted bandwidths are suppressed, and a reconfigurable filter is realized by using memristive switches. In addition, hardware for the automatic programming of KnowM's commercially available memristors has been designed, an algorithm and microcontroller software that enables automatic programming have been developed, as well as software for a portable or remote device to control the operation of the microcontroller. Electrical circuits designed using the commercially available memristor were realized. A frequency analysis model of the commercially available memristor at frequencies of up to 1 MHz has been proposed. An active bandpass filter has been designed, which has the ability to tune the center frequency during operation. Laboratory prototypes were made for the experimental verification of the operation of programmers and electrical circuits