Design and Analysis of a Novel Low Complexity and Low Power Ping Lock Arbiter by using EGDI based CMOS Technique

Network-on-chip (NoC) provides solution to overcome the complications of the on-chip interconnect architecture in multi-core systems. It mainly consists of router, links and network interface. An essential component of on-chip router is an arbiter that significantly impacts the performance of the router. The arbiter should provide fast and fair arbitration when it is placed in Critical Path Delay (CPD) systems. The main aim of this research work is to design a novel arbiter for an effective network scheduler in complex real time applications. At the same time resource allocation and power consumption should be very low. Previously, a novel gate level Ping Lock Arbiter (PLA) is designed to overcome the limited fair arbitration in Improved Ping Pong Arbiter (IPPA) with less delay. But the chip size and power consumption are very high. To overcome this problem, an Effective Gate Diffusion Input (EGDI) logic based CMOS scheme is used to design a novel Compact Ping Lock Arbiter (CPLA).  The proposed CPLA is compared with the existing PLA based on static CMOS scheme. The comparison between the conventional and proposed arbiter is carried out to analyze the area, delay and power by using Tanner Tool 14.1 with 250nm and 45nm. The results show that the proposed NPLA achieves low power and consumes less than the existing ping lock arbiter

FPGA-Based PUF Designs: A Comprehensive Review and Comparative Analysis

Field-programmable gate arrays (FPGAs) have firmly established themselves as dynamic platforms for the implementation of physical unclonable functions (PUFs). Their intrinsic reconfigurability and profound implications for enhancing hardware security make them an invaluable asset in this realm. This groundbreaking study not only dives deep into the universe of FPGA-based PUF designs but also offers a comprehensive overview coupled with a discerning comparative analysis. PUFs are the bedrock of device authentication and key generation and the fortification of secure cryptographic protocols. Unleashing the potential of FPGA technology expands the horizons of PUF integration across diverse hardware systems. We set out to understand the fundamental ideas behind PUF and how crucially important it is to current security paradigms. Different FPGA-based PUF solutions, including static, dynamic, and hybrid systems, are closely examined. Each design paradigm is painstakingly examined to reveal its special qualities, functional nuances, and weaknesses. We closely assess a variety of performance metrics, including those related to distinctiveness, reliability, and resilience against hostile threats. We compare various FPGA-based PUF systems against one another to expose their unique advantages and disadvantages. This study provides system designers and security professionals with the crucial information they need to choose the best PUF design for their particular applications. Our paper provides a comprehensive view of the functionality, security capabilities, and prospective applications of FPGA-based PUF systems. The depth of knowledge gained from this research advances the field of hardware security, enabling security practitioners, researchers, and designers to make wise decisions when deciding on and implementing FPGA-based PUF solutions.publishedVersio

Design Space Exploration and Resource Management of Multi/Many-Core Systems

The increasing demand of processing a higher number of applications and related data on computing platforms has resulted in reliance on multi-/many-core chips as they facilitate parallel processing. However, there is a desire for these platforms to be energy-efficient and reliable, and they need to perform secure computations for the interest of the whole community. This book provides perspectives on the aforementioned aspects from leading researchers in terms of state-of-the-art contributions and upcoming trends

Electronics for Sensors

The aim of this Special Issue is to explore new advanced solutions in electronic systems and interfaces to be employed in sensors, describing best practices, implementations, and applications. The selected papers in particular concern photomultiplier tubes (PMTs) and silicon photomultipliers (SiPMs) interfaces and applications, techniques for monitoring radiation levels, electronics for biomedical applications, design and applications of time-to-digital converters, interfaces for image sensors, and general-purpose theory and topologies for electronic interfaces

Low Power Memory/Memristor Devices and Systems

This reprint focusses on achieving low-power computation using memristive devices. The topic was designed as a convenient reference point: it contains a mix of techniques starting from the fundamental manufacturing of memristive devices all the way to applications such as physically unclonable functions, and also covers perspectives on, e.g., in-memory computing, which is inextricably linked with emerging memory devices such as memristors. Finally, the reprint contains a few articles representing how other communities (from typical CMOS design to photonics) are fighting on their own fronts in the quest towards low-power computation, as a comparison with the memristor literature. We hope that readers will enjoy discovering the articles within

Artificial Neural Network Design Approaches to Multi-Channel Information Analysis

In recent years, a large amount of multi-channel data has been collected due to advances in technology such as with computers and the Internet. However, obtaining and labelling data are still laborious and time-consuming. Yet another issue that adds to the difficulty is finding important channels and features from multi-channel data since having enough channels alone does not guarantee designing efficient algorithms due to scalability problems. In this thesis, a generative model and hierarchical learning models are introduced to deal with the aforementioned issues. First, the learning process of Variational Autoencoders is analysed. Taking into account the role of the mean and the standard deviation, which are used in the reparameterization trick, we propose a new generative model. The proposed model is modified from the original Autoencoder architecture which is used for dimensionality reduction. The model preserves the architecture of the Autoencoder by removing the reparameterization trick and becomes a generative model by extension of the mapping of the decoder from a discrete latent space to a continuous latent space. The model is compared with VAE and MMD on three benchmark datasets: MNIST, Fashion-MNIST and SVHN datasets. The experimental results show that the difference of the accuracy of the test set when training ANNs using synthetic data generated by the proposed model is less than 10% when training it using the original training set in MNIST and Fashion-MINST datasets. In addition, further experiments are carried out to investigate the impact of the number of the training set when training generative models. The results show that the accuracy of the test set decreases less than 10% when the number of the training set decreases in the NNIST and the Fashion-MNIST dataset. Second, two types of hierarchical learning models are proposed. Designing these models began with the idea of utilizing an innate hierarchy of targets. The first type of model, HAL, is proposed when targets are discrete. This model involves inserting the auxiliary block to output the auxiliary scores from the coarse classes. These scores are distributed based on the corresponding coarse classes. Although the model improves the accuracy of a test set, it has the disadvantage of requiring the coarse classes at the test phase. The second type of models are proposed when targets are continuous. C-FNNs and HADNNs are proposed to perform the regression task by utilizing the coarse classes. C-FNNs and HADNNs are evaluated on three benchmark indoor localization datasets, examples of multi-channel data. Results show that C-FNNs increase the floor accuracy by 30% at least and 60% at most in the three datasets. However, C-FNNs require more than three times the parameters than the baseline. HADNNs achieve better accuracy than C-FNNs and require 1.2 times the parameters than the baseline at most. Third, human motion data is analysed in order to show the importance of the relationship between sensor locations and motion types when identifying motion types. The data were gathered from patients and students in Inha University Hospital, Korea. Twenty-three subjects participated in the experiment and all had to perform nine motion types. Forty-eight total measurements were obtained from eight different body parts. The motion type detection algorithm is divided into five steps and is evaluated based on four metrics: recall, precision, accuracy and F-measure. The proposed detection algorithm has $0.8986$ average recall, 0.9071 average precision, 0.9739 average accuracy and 0.8977 average F-measure. The detection algorithm outperforms PCA, which is a popular method in feature extraction. This shows the importance of feature extraction based on the relationship between channels and targets in multi-channel data. Finally, the motion type detection process is proposed by integrating the proposed models. The process is divided into three: generation, labelling and classification. In generation, the proposed generative model is used to generate synthetic data. In labelling, SVM and PCA are used to label synthetic data. In classification, ResNet with C-FNNs and with HADNNs for a classification task are trained using the combination of the labelled synthetic data and the original training set, and the neural networks are used to detect motion types. The process is evaluated using InhaMotion and nine open source human motion datasets. The results show that training ANNs with synthetic data prevents overfitting, and the proposed generative model outperforms VAE, beta-VAE and MMD. In addition, the combination of ResNet and C-FNNs increase the accuracies of the test sets when coarse classes are available during the training phase. Since C-FNNs do not require coarse classes at the test phase, it is practical to use in daily life problems where hierarchy of targets should be considered

Metodologia para teste e análise de degradação de desempenho em protocolos de comunicação intra-veiculares

Considerar os efeitos de falhas e interferências que afetam as redes intra-veiculares desde o projeto dos seus sistemas de controle tornou-se fundamental, pois, a complexidade da eletrônica embarcada, o aumento do fluxo de informação e também as possibilidades de ataques maliciosos, tornaram o projeto destes sistemas uma tarefa cada vez mais complexa. Neste contexto, a presente tese visa explorar formas de integrar e modelar os efeitos de degradação causados por diferentes tipos de falhas que afetam os protocolos de comunicação, na interconexão das unidades de controle eletrônicas (ECUs). Dentre estas falhas, a pesquisa destaca o estudo aprofundado dos transientes elétricos rápidos – EFT, que degradam o desempenho e geram efeitos como perda de pacotes e atrasos de comunicação. Desta forma, contribui-se com uma metodologia para o tratamento de falhas em sistemas críticos de tempo real, desde as fases iniciais do projeto, utilizando a modelagem orientada a aspectos para modelar e especificar requisitos do sistema, de acordo com características transversais dos requisitos não funcionais relacionados a falhas. Para a definição dos requisitos não funcionais, esta pesquisa usa como base o framework RTFRIDA (Real-Time From Requirements to Design using Aspects), o qual foi estendido para agregar com mais detalhes a modelagem de falhas. Para fins de validação da metodologia foi desenvolvido um mecanismo de diagnóstico de degradação de desempenho, o qual foi integrado a um sistema de controle de suspensão ativa. O estudo foi avaliado em diferentes cenários de carga da rede e com injeções de falhas usando dois tipos de hardwares que seguem normas de teste usadas na indústria. Os resultados evidenciaram a aplicabilidade da metodologia, com a modelagem de um mecanismo de diagnóstico que detectou e registrou os distúrbios de desempenho nos cenários estudados. As análises enfatizam a degradação de desempenho acentuada registrada com as injeções EFT de maior amplitude de tensão e menor tempo de rajada, com carga de ocupação da rede acima de 30%. Os experimentos avaliaram o desempenho dos atuais protocolos de comunicação, com melhores resultados obtidos em FlexRay e CAN-FD, o que confirma a evolução dos protocolos para atender as recentes demandas de desempenho da indústria automotiva.Embedded computing applications are increasingly demanding performance and reliability because these factors are critical to the safety of real-time systems. Reliability aspects in design phases is a fundamental point of many researches because with the increase of embedded electronics, network data transmission and also possibilities of attacks on them, make the design of these systems an increasingly complex task. The present thesis aims to explore and correlate different fault types that degrade vehicular communication protocols performance used to interconnect embedded control units (ECUs). Among these faults, the electrical fast transients - EFT are highlighted, since they generate effects such as packet loss and communication delays. Thus, a methodology based on aspect-oriented modeling concepts, in real-time critical systems is proposed, to model and specify system requirements according to cross-cutting concerns of non-functional requirements related to faults. For non-functional requirements specification, this work is based on RT-FRIDA (Real-Time From Requirements to Design using Aspects) framework, which was be extended for fault modeling. Thus, the novel methodology allows fault modeling following the aspect-oriented principles from the early design phases. For the methodology validation purposes, a performance degradation diagnostic mechanism was developed, which was integrated into an active suspension control system. The study was evaluated in different network busload scenarios and with fault injections using two hardware types, certified by standards used in the automotive industry. The results present that the developed mechanism detected performance disturbances, recording occurrence data in the studied scenarios. The analyzes emphasize the best performance degradation observed with EFT injection of higher voltage amplitude, shorter burst time, and busload above 30%. The experiments evaluated the performance of current communication protocols, with better results obtained in FlexRay and CAN-FD, which confirms the protocol’s evolution to meet the recent performance demands of the automotive industry