A linear high-efficiency millimeter-wave CMOS Doherty radiator leveraging on-antenna active load-modulation

This thesis presents a Doherty Radiator architecture that explores multi-feed antennas to achieve an on-antenna Doherty load modulation network and demonstrate high-speed high-efficiency transmission of wideband modulated signals. On the passive circuits, we exploit the multi-feed antenna concept to realize compact and high-efficiency on-antenna active load modulation for close-to-ideal Doherty operation, on-antenna power combining, and mm-Wave signal radiation. Moreover, we analyze the far-field transmission of the proposed Doherty Radiator and demonstrate its wide Field-of-View (FoV). On the active circuits, we employ a GHz-bandwidth adaptive biasing at the Doherty Auxiliary power amplifier (PA) path to enhance the Main/Auxiliary Doherty cooperation and appropriate turning-on/-off of the Auxiliary path. A proof-of-concept Doherty Radiator implemented in a 45nm CMOS SOI process over 62-68GHz exhibits a consistent 1.45-1.53× PAE enhancement at 6dB PBO over an idealistic class-B PA with the same PAE at P1dB. The measured Continuous-Wave (CW) performance at 65GHz demonstrates 19.4/19.2dBm PSAT/P1dB and achieves 27.5%/20.1% PAE at peak/6dB PBO, respectively. For single-carrier 1Gsym/s 64-QAM modulation, the Doherty Radiator shows average output power of 14.2dBm with an average 20.2% PAE and -26.7dB EVM without digital predistortion. Consistent EVMs are observed over the entire antenna FoV, demonstrating spatially undistorted transmission and constant Doherty PBO efficiency enhancement.M.S

Reconfigurable Receiver Front-Ends for Advanced Telecommunication Technologies

The exponential growth of converging technologies, including augmented reality, autonomous vehicles, machine-to-machine and machine-to-human interactions, biomedical and environmental sensory systems, and artificial intelligence, is driving the need for robust infrastructural systems capable of handling vast data volumes between end users and service providers. This demand has prompted a significant evolution in wireless communication, with 5G and subsequent generations requiring exponentially improved spectral and energy efficiency compared to their predecessors. Achieving this entails intricate strategies such as advanced digital modulations, broader channel bandwidths, complex spectrum sharing, and carrier aggregation scenarios. A particularly challenging aspect arises in the form of non-contiguous aggregation of up to six carrier components across the frequency range 1 (FR1). This necessitates receiver front-ends to effectively reject out-of-band (OOB) interferences while maintaining high-performance in-band (IB) operation. Reconfigurability becomes pivotal in such dynamic environments, where frequency resource allocation, signal strength, and interference levels continuously change. Software-defined radios (SDRs) and cognitive radios (CRs) emerge as solutions, with direct RF-sampling receivers offering a suitable architecture in which the frequency translation is entirely performed in digital domain to avoid analog mixing issues. Moreover, direct RF- sampling receivers facilitate spectrum observation, which is crucial to identify free zones, and detect interferences. Acoustic and distributed filters offer impressive dynamic range and sharp roll off characteristics, but their bulkiness and lack of electronic adjustment capabilities limit their practicality. Active filters, on the other hand, present opportunities for integration in advanced CMOS technology, addressing size constraints and providing versatile programmability. However, concerns about power consumption, noise generation, and linearity in active filters require careful consideration.This thesis primarily focuses on the design and implementation of a low-voltage, low-power RFFE tailored for direct sampling receivers in 5G FR1 applications. The RFFE consists of a balun low-noise amplifier (LNA), a Q-enhanced filter, and a programmable gain amplifier (PGA). The balun-LNA employs noise cancellation, current reuse, and gm boosting for wideband gain and input impedance matching. Leveraging FD-SOI technology allows for programmable gain and linearity via body biasing. The LNA's operational state ranges between high-performance and high-tolerance modes, which are apt for sensitivityand blocking tests, respectively. The Q-enhanced filter adopts noise-cancelling, current-reuse, and programmable Gm-cells to realize a fourth-order response using two resonators. The fourth-order filter response is achieved by subtracting the individual response of these resonators. Compared to cascaded and magnetically coupled fourth-order filters, this technique maintains the large dynamic range of second-order resonators. Fabricated in 22-nm FD-SOI technology, the RFFE achieves 1%-40% fractional bandwidth (FBW) adjustability from 1.7 GHz to 6.4 GHz, 4.6 dB noise figure (NF) and an OOB third-order intermodulation intercept point (IIP3) of 22 dBm. Furthermore, concerning the implementation uncertainties and potential variations of temperature and supply voltage, design margins have been considered and a hybrid calibration scheme is introduced. A combination of on-chip and off-chip calibration based on noise response is employed to effectively adjust the quality factors, Gm-cells, and resonance frequencies, ensuring desired bandpass response. To optimize and accelerate the calibration process, a reinforcement learning (RL) agent is used.Anticipating future trends, the concept of the Q-enhanced filter extends to a multiple-mode filter for 6G upper mid-band applications. Covering the frequency range from 8 to 20 GHz, this RFFE can be configured as a fourth-order dual-band filter, two bandpass filters (BPFs) with an OOB notch, or a BPF with an IB notch. In cognitive radios, the filter’s transmission zeros can be positioned with respect to the carrier frequencies of interfering signals to yield over 50 dB blocker rejection

CMOS MESFET Cascode Amplifiers for RFIC Applications

abstract: There is an ever-increasing demand for higher bandwidth and data rate ensuing from exploding number of radio frequency integrated systems and devices. As stated in the Shannon-Hartley theorem, the maximum achievable data rate of a communication channel is linearly proportional to the system bandwidth. This is the main driving force behind pushing wireless systems towards millimeter-wave frequency range, where larger bandwidth is available at a higher carrier frequency. Observing the Moor’s law, highly scaled complementary metal–oxide–semiconductor (CMOS) technologies provide fast transistors with a high unity power gain frequency which enables operating at millimeter-wave frequency range. CMOS is the compelling choice for digital and signal processing modules which concurrently offers high computation speed, low power consumption, and mass integration at a high manufacturing yield. One of the main shortcomings of the sub-micron CMOS technologies is the low breakdown voltage of the transistors that limits the dynamic range of the radio frequency (RF) power blocks, especially with the power amplifiers. Low voltage swing restricts the achievable output power which translates into low signal to noise ratio and degraded linearity. Extensive research has been done on proposing new design and IC fabrication techniques with the goal of generating higher output power in CMOS technology. The prominent drawbacks of these solutions are an increased die area, higher cost per design, and lower overall efficiency due to lossy passive components. In this dissertation, CMOS compatible metal–semiconductor field-effect transistor (MESFETs) are utilized to put forward a new solution to enhance the power amplifier’s breakdown voltage, gain and maximum output power. Requiring no change to the conventional CMOS process flow, this low cost approach allows direct incorporation of high voltage power MESFETs into silicon. High voltage MESFETs were employed in a cascode structure to push the amplifier’s cutoff frequency and unity power gain frequency to the 5G and K-band frequency range. This dissertation begins with CMOS compatible MESFET modeling and fabrication steps, and culminates in the discussion of amplifier design and optimization methodology, parasitic de-embedding steps, simulation and measurement results, and high resistivity RF substrate characterization.Dissertation/ThesisDoctoral Dissertation Electrical Engineering 201

Study and design of an impulse radio UWB synthesizer for 3.1-10.6 GHz band in 28 NM CMOS FD-SOI technology

Orientador: Prof. Ph.D. André Augusto MarianoCoorientador: Prof. Ph.D. Rémy VaucheDissertação (mestrado) - Universidade Federal do Paraná, Setor de Tecnologia, Programa de Pós-Graduação em Engenharia Elétrica. Defesa : Curitiba, 21/03/2022Inclui referências: p. 107-110Resumo: Este trabalho de dissertação de mestrado apresenta o estudo e desenvolvimento de sintetizador de pulsos de radio ultra banda larga para a banda 3,1-10,6 GHz em tecnologia 28 nm CMOS FD-SOI. A primeira utilização dessa banda de frequência foi autorizada pela comissão federal de comunicações dos Estados Unidos em 2002. Visando a explorar essa banda de frequência, o padrão IEEE 802.15.4 escolheu as comunicações baseadas em pulsos de radio em detrimento das comunicações tradicionais de banda estreita. Uma linha importante de pesquisa e o estudo e desenvolvimento de um transmissor ultra banda larga, capaz de endereçar múltiplas bandas e múltiplos padrões diferentes, que e consistido em um sintetizador de pulsos de radio devendo ter a capacidade de cobrir a banda 3,1-10,6 GHz. Para atingir tal objetivo, visa-se a implementação de uma arquitetura versátil baseada em um gerador de pulsos constituído principalmente por um oscilador controlado por tensão, e um circuito de formatação da envoltória do pulso, em que e possível fazer ajuste da duração e da frequência central dos pulsos, e compensar variações PVT (Processo, Tensão e Temperatura). O objetivo principal deste trabalho de dissertação de mestrado e estudo e desenvolvimento de um sintetizador de pulsos baseado nessa arquitetura em tecnologia 28 nm CMOS FD-SOI, de maneira que esse circuito seja capaz de cobrir toda banda 3.1-10.6 GHz e ao mesmo tempo cumprir os requerimentos espectrais estabelecidos pelos padrões IEEE 802.15.4 e IEEE 802.15.6. No projeto do circuito proposto, utilizou-se a técnica de síntese de pulso por transposição de frequência, constituído principalmente por um oscilador local comutado, permitindo a redução do consumo de energia, em que o sinal produzido pelo oscilador e modulado por um pulso em banda base. Em relação a metodologia do projeto, trata-se de um projeto totalmente personalizado, em que se utilizou as logicas CMOS e CML (Logica Diferencial), e se considerou capacitâncias parasitas estimadas no intuito de melhorar o dimensionamento dos transistores. A arquitetura do oscilador escolhida neste projeto foi o oscilador em anel, a qual permite de se obter uma banda de frequência suficientemente alta. Acerca da formatação do pulso, escolheu-se uma envoltória possível de se implementar com circuito digital reprogramável, visando a endereçar os diferentes canais do padrão IEEE 802.15.4 e IEEE 802.15.6. O sistema implementado, em nível de esquemático de transistor considerando capacitâncias parasitas estimadas, apresenta um desempenho satisfatório sobre a toda a banda de frequência de interesse, em que os pulsos gerados respeitam os gabaritos espectrais impostos pelos padrões IEEE, evidenciando a capacidade do circuito prosposto de ser multi-banda e cobrir toda a banda de frequência de interesse. Em relação ao consumo de potência, esse e influenciado pela duração do pulso e sua frequência central. Ademais, obteve-se um consumo de potencia estática 14 µW e um consumo de energia por pulso emitido máximo de 308 pJ, em que para esse caso, o pulso apresenta um energia transmitida de 11,7 pJ por pulso, assim apresentando uma eficiência de 3,8 %.Abstract: This dissertation work concerns the study and design of an impulse radio ultra-wide band synthesizer for 3.1-10.6 GHz frequency band in 28 nm CMOS FD-SOI technology. Indeed, this frequency band exploitation was initially authorized by the federal communications commission of United States in 2002. Targeting to exploit this frequency band, the IEEE 802.15.4 standard has chosen the communications based on impulse radio instead of the traditional narrowband communications. Besides, the impulse radio communications should respect communications standards, like the IEEE 802.15.4 for wireless personal networks, or IEEE 802.15.6 for wireless body networks. These IEEE standards define the generated pulse bandwidth and its central frequency. An important line of research is the study and design of a multi-standard or multi-band UWB transmitter, consisted by a pulse synthesizer that should be able to address all the standardized channels. To accomplish this, a proposed solution reposes on design of versatile architecture based on pulse generator and an envelope shaping circuit, where it is possible to tune the pulse duration and central frequency, and also to compensate PVT variations (Process, Voltage and Temperature). The dissertation work main goal is the study and design of a pulse synthesizer based on this architecture in 28 nm CMOS FD-SOI technology, such that the designed system is capable to cover all the 3.1-10.6 GHz and at same time to comply the spectral requirements established by IEEE 802.15.4 and 802.15.6 standards. In relation of the proposed circuit design, it is applied the pulse synthesis technique based on frequency transposition, that is mainly composed by a local oscillator that can be turned on and off, which allows to reduce the power consumption. The generated oscillation is modulated by a baseband pulse. Concerning the design methodology, it is a full-custom project, where CMOS and CML logics were used, and estimated parasitic capacitances were considered to achieve more reliable transistor sizing. The oscillator architecture chosen is based on ring oscillator, which allows to reach a frequency range sufficiently large. For the pulse shaping, it was chosen a envelope that is feasible to implement with fully digital circuit, targeting to address all IEEE 802.15.4 and IEEE 802.15.6 standard channels. The implemented system presents, in schematic levels considering parasitic capacitances, a satisfactory performance over all the 3.1-10.6 GHz band, where the generated pulses respect the spectral requirements imposed by the IEEE standards, therefore indicating that the proposed circuit is multi-band and able to cover all frequency band of interest. In terms of power consumption, it was achieved a power leakage of 14 µW and a maximal energy per pulse consumption of 308 pJ, where for this case, the pulse has an emitted energy of 11.7 pJ per pulse, therefore a efficiency of 3.8 %