Oxygen-insertion Technology for CMOS Performance Enhancement

Until 2003, the semiconductor industry followed Dennard scaling rules to improve complementary metal-oxide-semiconductor (CMOS) transistor performance. However, performance gains with further reductions in transistor gate length are limited by physical effects that do not scale commensurately with device dimensions: short-channel effects (SCE) due to gate-leakage-limited gate-oxide thickness scaling, channel mobility degradation due to enhanced vertical electric fields, increased parasitic resistances due to reductions in source/drain (S/D) contact area, and increased variability in transistor performance due to random dopant fluctuation (RDF) effects and gate work function variations (WFV). These emerging scaling issues, together with increased process complexity and cost, pose severe challenges to maintaining the exponential scaling of transistor dimensions. This dissertation discusses the benefits of oxygen-insertion (OI) technology, a CMOS performance booster, for overcoming these challenges. The benefit of OI technology to mitigate the increase in sheet resistance ($R_{sh}$) with decreasing junction depth ($X_J$) for ultra-shallow-junctions (USJs) relevant for deep-sub-micron planar CMOS transistors is assessed through the fabrication of $R_{sh}$ test structures, electrical characterization, and technology computer-aided design (TCAD) simulations. Experimental and secondary ion mass spectroscopy (SIMS) analyses indicate that OI technology can facilitate low-resistivity USJ formation by reducing $R_{sh}$ and $X_J$ due to retarded transient-enhanced-diffusion (TED) effects and enhanced dopant retention during post-implantation thermal annealing. It is also shown that a low-temperature-oxide (LTO) capping can increase $R_{sh}$ unfavorably due to lower dopant activation levels, which can be alleviated by OI technology. This dissertation extends the evaluation of OI technology to advanced FinFET technology, targeting 7/8-nm low power technology node. A bulk-Si FinFET design comprising a super-steep retrograde (SSR) fin channel doping profile achievable with OI technology is studied by three-dimensional (3-D) TCAD simulations. As compared with the conventional bulk-Si (control) FinFET design with a heavily-doped fin channel doping profile, SSR FinFETs can achieve higher $I_{on}/I_{off}$ ratios and reduce the sensitivity of device performance to variations due to the lightly doped fin channel. As compared with the SOI FinFET design, SSR FinFETs can achieve similarly low $V_{DD,min}$ for 6T-SRAM cell yield estimation. Both SSR and SOI design can provide for as much as 100 mV reduction in $V_{DD,min}$ compared with the control FinFET design. Overall, the SSR FinFET design that can be achieved with OI technology is demonstrated to be a cheaper alternative to the SOI FinFET technology for extending CMOS scaling beyond the 10-nm node. Finally, this dissertation investigates the benefits of OI technology for reducing the Schottky barrier height ($\Phi_{Bp}$) of a Pt/Ti/p-type Si metal-semiconductor (M/S) contact, which can be expected to help reduce the specific contact resistivity for a p-type silicon contact. Electrical measurements of back-to-back Schottky diodes, SIMS, and X-ray photoelectron spectroscopy (XPS) show that the reduction in $\Phi_{Bp}$ is associated with enhanced Ti 2p and Si 2p core energy level shifts. OI technology is shown to favor low-$\Phi_{Bp}$ Pt monosilicide formation during forming gas anneal (FGA) by suppressing the grain boundary diffusion of Pt atoms into the crystalline Si substrate

Développement de modèles pour l'évaluation des performances circuit des technologies CMOS avancées sub-20nm

Depuis la commercialisation du premier circuit intégré en 1971, l'industrie de la microélectronique s'est fixée comme leitmotiv de réduire les dimensions des transistors MOSFETs, en suivant la loi de Moore. Comme indiqué par Dennard, cette miniaturisation améliore automatiquement les performances des transistors. A partir des nœuds 28-22nm, les effets canaux courts sont trop difficiles à contrôler et de nouvelles architectures de transistors sont introduites: FDSOI pour STMicroelectronics, Trigate pour Intel. Dans ce contexte, l'évaluation des performances des technologies CMOS est clé et les travaux de cette thèse proposent de les évaluer au niveau circuit. Des modèles spécifiques d'estimation des paramètres électrostatiques et des capacités parasites sont développés. Ceux-ci sont d'abord utilisés sur des technologies amonts (co-intégration III-V/Ge et intégration 3D) puis sont implémentés en VerilogA pour être utilisés avec les outils conventionnel de CAO. Ceci fournit un modèle compact prédictif et utilisable pour toutes les architectures CMOS, qui est utilisé pour évaluer les performances logiques et SRAM des architectures BULK, FDSOI et Trigate aux nœuds 20nm et 16nm.Since the commercialization of the first integrated circuit in 1971, the microelectronic industry has fixed as an objective to reduce MOSFET transistor dimensions, following Moore's law. As indicated by Dennard, this miniaturization automatically improves device performances. Starting from the 28-22nm technological nodes, short channel effects are to strong and industrial companies choose to introduce new device structure: FDSOI for STMicroelectronics and Trigate for Intel. In such a context, CMOS technology performance evaluation is key and this thesis proposes to evaluate them at circuit level. Specific models for electrostatic parameters and parasitic capacitances for each device structure are developed for each device structure. Those models have first been used to evaluate performances of advanced technologies, such as III-V/Ge co-integration and 3D monolithic integration and have then been implemented in VerilogA to ensure compatibility with conventional CAD tools such as ELDO. This provides a compact model, predictive and usable for each device structure, which has been used to evaluated logic and SRAM performances of BULK, FDSOI and Trigate devices for the 20nm and 16nm technology node.SAVOIE-SCD - Bib.électronique (730659901) / SudocGRENOBLE1/INP-Bib.électronique (384210012) / SudocGRENOBLE2/3-Bib.électronique (384219901) / SudocSudocFranceF

Simulation and Modeling of Silicon Based Emerging Nanodevices: From Device to Circuit Level

Nanostructure based devices are very promising candidates for the emerging nanotechnologies with advantage in terms of power consumption and functional density. Nanowire Field Effect Transistor (NWFET) and Single Electron Transistor (SET) are the focus of this work. The serious challenges faced by the MOSFET due to scaling limits can be solved by these devices. NWFET provides better gate control and overcomes the short channel effects. SET operates in the quantum confinement regime where the basic operation of MOSFET becomes a challenge. SET works better when the dimensions are small encouraging the process of scaling down. Because of these characteristics of the nanodevices, they have achieved a huge interest from the viewpoint of theoretical as well as applied electronics. The studies focus on the understanding of the basic transport characteristics of the devices. The necessity is to develop a model which is efficient, can be used at circuit level and also provides physical insights of the device. The first part of this work focuses on developing the model for SET and to implement it at the circuit level. The transport properties of SET are studied through quantum simulations. The behavioral characterization of the device is performed and the effect of different device parameters on the transport is studied. Furthermore, the impact of gate voltage is analyzed which modulates the current by shifting the energy levels of the device. After observing the transport through SET, a model is developed that efficiently evaluates the IV characteristics of the device. The quantum simulations are used as reference and a huge computational over-head is achieved while maintaining accuracy. Then the model is implemented in hardware descriptive language showing its functional variability at circuit level by designing some logic circuits like AND, OR and FA. In the second part, the performance of the nanoarrays based on NWFET is characterized. A device level model is developed to evaluate the gate capacitance and drain current of NWFET. Starting from the output of the model, in-house simulator is modified and used to evaluate the switching activity of the devices in nanoarray. A nanoarray implementation for bio-sequence alignment based on a systolic array is realized and its essential performance is evaluated. The power consumption, area and performance of the nanoarray implementation are compared with CMOS implementation. A wide solution space can be explored to find the optimal solution trading power and performance and considering the technological limitations of a realistic implementation

Double-gate single electron transistor : modeling, design & evaluation of logic architectures

Dans les années à venir, l'industrie de la microélectronique doit développer de nouvelles filières technologiques qui pourront devenir des successeurs ou des compléments de la technologie CMOS ultime. Parmi ces technologies émergentes relevant du domaine « Beyond CMOS », ce travail de recherche porte sur les transistors mono-électroniques (SET) dont le fonctionnement est basé sur la quantification de la charge électrique, le transport quantique et la répulsion Coulombienne. Les SETs doivent être étudiés à trois niveaux : composants, circuits et système. Ces nouveaux composants, utilisent à leur profit le phénomène dit de blocage de Coulomb permettant le transit des électrons de manière séquentielle, afin de contrôler très précisément le courant véhiculé. En effet, l'émergence du caractère granulaire de la charge électrique dans le transport des électrons par effet tunnel, permet d'envisager la réalisation de remplaçants potentiels des transistors ou de cellules mémoire à haute densité d'intégration, basse consommation. L'objectif principal de ce travail de thèse est d'explorer et d'évaluer le potentiel des transistors mono-électroniques double-grille métalliques (DG-SETs) pour les circuits logiques numériques. De ce fait, les travaux de recherches proposés sont divisés en trois parties : i) le développement des outils de simulation et tout particulièrement un modèle analytique de DG-SET ; ii) la conception de circuits numériques à base de DG-SETs dans une approche « cellules standards » ; et iii) l'exploration d'architectures logiques versatiles à base de DG-SETs en exploitant la double-grille du dispositif. Un modèle analytique pour les DG-SETs métalliques fonctionnant à température ambiante et au-delà est présenté. Ce modèle est basé sur des paramètres physiques et géométriques et implémenté en langage Verilog-A. Il est utilisable pour la conception de circuits analogiques ou numériques hybrides SET-CMOS. A l'aide de cet outil, nous avons conçu, simulé et évalué les performances de circuits logiques à base de DG-SETs afin de mettre en avant leur utilisation dans les futurs circuits ULSI. Une bibliothèque de cellules logiques, à base de DG-SETs, fonctionnant à haute température est présentée. Des résultats remarquables ont été atteints notamment en termes de consommation d'énergie. De plus, des architectures logiques telles que les blocs élémentaires pour le calcul (ALU, SRAM, etc.) ont été conçues entièrement à base de DG-SETs. La flexibilité offerte par la seconde grille du DG-SET a permis de concevoir une nouvelle famille de circuits logiques flexibles à base de portes de transmission. Une réduction du nombre de transistors par fonction et de consommation a été atteinte. Enfin, des analyses Monte-Carlo sont abordées afin de déterminer la robustesse des circuits logiques conçus à l'égard des dispersions technologiques

Techniques of Energy-Efficient VLSI Chip Design for High-Performance Computing

How to implement quality computing with the limited power budget is the key factor to move very large scale integration (VLSI) chip design forward. This work introduces various techniques of low power VLSI design used for state of art computing. From the viewpoint of power supply, conventional in-chip voltage regulators based on analog blocks bring the large overhead of both power and area to computational chips. Motivated by this, a digital based switchable pin method to dynamically regulate power at low circuit cost has been proposed to make computing to be executed with a stable voltage supply. For one of the widely used and time consuming arithmetic units, multiplier, its operation in logarithmic domain shows an advantageous performance compared to that in binary domain considering computation latency, power and area. However, the introduced conversion error reduces the reliability of the following computation (e.g. multiplication and division.). In this work, a fast calibration method suppressing the conversion error and its VLSI implementation are proposed. The proposed logarithmic converter can be supplied by dc power to achieve fast conversion and clocked power to reduce the power dissipated during conversion. Going out of traditional computation methods and widely used static logic, neuron-like cell is also studied in this work. Using multiple input floating gate (MIFG) metal-oxide semiconductor field-effect transistor (MOSFET) based logic, a 32-bit, 16-operation arithmetic logic unit (ALU) with zipped decoding and a feedback loop is designed. The proposed ALU can reduce the switching power and has a strong driven-in capability due to coupling capacitors compared to static logic based ALU. Besides, recent neural computations bring serious challenges to digital VLSI implementation due to overload matrix multiplications and non-linear functions. An analog VLSI design which is compatible to external digital environment is proposed for the network of long short-term memory (LSTM). The entire analog based network computes much faster and has higher energy efficiency than the digital one

Nouvelles Architectures Hybrides (Logique / Mémoires Non-Volatiles et technologies associées.)

Les nouvelles approches de technologies mémoires permettront une intégration dite back-end, où les cellules élémentaires de stockage seront fabriquées lors des dernières étapes de réalisation à grande échelle du circuit. Ces approches innovantes sont souvent basées sur l'utilisation de matériaux actifs présentant deux états de résistance distincts. Le passage d'un état à l'autre est contrôlé en courant ou en tension donnant lieu à une caractéristique I-V hystérétique. Nos mémoires résistives sont composées d'argent en métal électrochimiquement actif et de sulfure amorphe agissant comme électrolyte. Leur fonctionnement repose sur la formation réversible et la dissolution d'un filament conducteur. Le potentiel d'application de ces nouveaux dispositifs n'est pas limité aux mémoires ultra-haute densité mais aussi aux circuits embarqués. En empilant ces mémoires dans la troisième dimension au niveau des interconnections des circuits logiques CMOS, de nouvelles architectures hybrides et innovantes deviennent possibles. Il serait alors envisageable d'exploiter un fonctionnement à basse énergie, à haute vitesse d'écriture/lecture et de haute performance telles que l'endurance et la rétention. Dans cette thèse, en se concentrant sur les aspects de la technologie de mémoire en vue de développer de nouvelles architectures, l'introduction d'une fonctionnalité non-volatile au niveau logique est démontrée par trois circuits hybrides: commutateurs de routage non volatiles dans un Field Programmable Gate Arrays, un 6T-SRAM non volatile, et les neurones stochastiques pour un réseau neuronal. Pour améliorer les solutions existantes, les limitations de la performances des dispositifs mémoires sont identifiés et résolus avec des nouveaux empilements ou en fournissant des défauts de circuits tolérants.Novel approaches in the field of memory technology should enable backend integration, where individual storage nodes will be fabricated during the last fabrication steps of the VLSI circuit. In this case, memory operation is often based upon the use of active materials with resistive switching properties. A topology of resistive memory consists of silver as electrochemically active metal and amorphous sulfide acting as electrolyte and relies on the reversible formation and dissolution of a conductive filament. The application potential of these new memories is not limited to stand-alone (ultra-high density), but is also suitable for embedded applications. By stacking these memories in the third dimension at the interconnection level of CMOS logic, new ultra-scalable hybrid architectures becomes possible which exploit low energy operation, fast write/read access and high performance with respect to endurance and retention. In this thesis, focusing on memory technology aspects in view of developing new architectures, the introduction of non-volatile functionality at the logic level is demonstrated through three hybrid (CMOS logic ReRAM devices) circuits: nonvolatile routing switches in a Field Programmable Gate Array, nonvolatile 6T-SRAMs, and stochastic neurons of an hardware neural network. To be competitive or even improve existing solutions, limitations on the memory devices performances are identified and solved by stack engineering of CBRAM devices or providing faults tolerant circuits.SAVOIE-SCD - Bib.électronique (730659901) / SudocGRENOBLE1/INP-Bib.électronique (384210012) / SudocGRENOBLE2/3-Bib.électronique (384219901) / SudocSudocFranceF

The study of weak ferromagnetism by andreev reflection spin spectroscopy and development of bimorph electro-thermal actuators

It is well accepted that spin polarization of materials has a major role in spintronics to improve the efficiency of spintronic devices. Point contact Andreev reflection (PCAR) spectroscopy, one of the most popular and reliable techniques, was used to obtain the conductance and by analyzing them by modified BTK model, spin polarizations of various materials, generally with low ferromagnetism, were extracted in order to understand the transport properties of spin polarized current and find the relation of spin polarization with other parameters such as saturation magnetization or the Curie temperature so that better spintronic materials can be identified and developed. We investigated how the spin polarization of itinerant ferromagnet MnSi changes as it undergoes magnetic phase transition from helical to conical to induced ferromagnetic. Also, unconventional conductance with enhanced Andreev reflection with amplitude more than two, and conductance oscillations outside superconducting gap indicate the signature of triplet superconductivity in Nb/MnSi contacts made by e-beam lithography and sputtering. Another system studied was Pd1-xNix which is an example of the strong ferromagnetic susceptibility enhancement of nearly ferromagnetic Pd by Ni impurities. The transport spin polarizations of Pd1-xNix with different Ni concentrations were measured and their correlation with saturation magnetization was studied. PCAR was applied to a superconducting sample: Co doped BaFe2As2 which revealed the presence of pseudogap in this material. Studies by SQUID, PCAR and neutron scattering, Pt thin films were found ferromagnetic which was supported by the first principle calculation indicating that its source is the surface roughness of the films, and the surface magnetization is more or less independent of the film thickness. MnBi of stable phase and high Curie temperature showed high perpendicular anisotropy and high transport spin polarization (P) which was found to be due to disparity in Fermi velocity in electron split bands. Their P is proportional to saturation magnetization, and this material is a potential candidate for spin injection to semiconductors. Room temperature ferromagnetism and finite low temperature spin polarization was observed in dilute magnetic semiconductor: undoped and Cr doped InN thin films so that it is another potential material for spintronic devices. Unlike predicted spin torque in FM/NM hybrid structure, freestanding Si3N4 microstructures with coating of Au or Ag or Ni showed torsion while passing dc current. The quadratic dependence of the torsion angles with the dc current were measured and such effect was accounted for the Joule heating of the metal coating and the residual strain of Si3N4 structures. Such electro-thermal actuators could find applications in MEMS technology