0.5V 3rd-order Tunable gm-C Filter

This paper proposes a 3rd-order gm-C filter that operates with the extremely low voltage supply of 0.5V. The employed transconductor is capable for operating in an extremely low voltage power supply environment. A benefit offered by the employed transconductor is that the filter’s cut-off frequency can be tuned, through a dc control current, for relatively large ranges. The filter structure was designed using normal threshold transistors of a triple-well 0.13μm CMOS process and is operated under a 0.5V supply voltage; its behavior has been evaluated through simulation results by utilizing the Analog Design Environment of the Cadence software

The design of active resistors and transductors in a CMOS technology

Merged with duplicate record 10026.1/2618 on 07.20.2017 by CS (TIS)This thesis surveys linearisation techniques for implementing monolithic MOS active resistors and transconductors, and investigates the design of linear tunable resistors and transconductors. Improving linearity and tunability in the presence of non-ideal factors such as bulk modulation, mobility-degradation effects and mismatch of transistors is a principal objective. A family of new non-saturation-mode resistors and two novel saturation-mode transconductors are developed. Where possible, approximate analytical expressions are derived to explain the principles of operation. Performance comparisons of the new structures are made with other well-known circuits and their relative advantages and disadvantages evaluated. Experimental and simulation results are presented which validate the proposed linearisation techniques. It is shown that the proposed family of resistors offers improved linearity whilst the transconductors combine extended tunability with low distortion. Continuous-time filter examples are given to demonstrate the potential of these circuits for application in analogue signal-processing tasks.GEC Plessey Semiconductors, Plymout

Unconventional Circuit Elements for Ladder Filter Design

Kmitočtové filtry jsou lineární elektrické obvody, které jsou využívány v různých oblastech elektroniky. Současně tvoří základní stavební bloky pro analogové zpracování signálů. V poslední dekádě bylo zavedeno množství aktivních stavebních bloků pro analogové zpracování signálů. Stále však existuje potřeba vývoje nových aktivních součástek, které by poskytovaly nové možnosti a lepší parametry. V práci jsou diskutovány různé aspekty obvodů pracujících v napěťovém, proudovém a smíšném módu. Práce reaguje na dnešní potřebu nízkovýkonových a nízkonapěťových aplikací pro přenosné přístroje a mobilní komunikační systémy a na problémy jejich návrhu. Potřeba těchto výkonných nízkonapěťových zařízení je výzvou návrhářů k hledání nových obvodových topologií a nových nízkonapěťových technik. V práci je popsána řada aktivních prvků, jako například operační transkonduktanční zesilovač (OTA), proudový konvejor II. generace (CCII) a CDTA (Current Differencing Transconductance Amplifier). Dále jsou navrženy nové prvky, jako jsou VDTA (Voltage Differencing Transconductance Amplifier) a VDVTA (Voltage Differencing Voltage Transconductance Amplifier). Všechny tyto prvky byly rovněž implementovány pomocí "bulk-driven" techniky CMOS s cílem realizace nízkonapěťových aplikací. Tato práce je rovněž zaměřena na náhrady klasických induktorů syntetickými induktory v pasivních LC příčkových filtrech. Tyto náhrady pak mohou vést k syntéze aktivních filtrů se zajímavými vlastnostmi.Frequency filters are linear electric circuits that are used in wide area of electronics. They are also the basic building blocks in analogue signal processing. In the last decade, a huge number of active building blocks for analogue signal processing was introduced. However, there is still the need to develop new active elements that offer new possibilities and better parameters. The current-, voltage-, or mixed-mode analog circuits and their various aspects are discussed in the thesis. This work reflects the trend of low-power (LP) low-voltage (LV) circuits for portable electronic and mobile communication systems and the problems of their design. The need for high-performance LV circuits encourages the analog designers to look for new circuit architectures and new LV techniques. This thesis presents various active elements such as Operational Transconductance Amplifier (OTA), Current Conveyor of Second Generation (CCII), and Current Differencing Transconductance Amplifier (CDTA), and introduces novel ones, such as Voltage Differencing Transconductance Amplifier (VDTA) and Voltage Differencing Voltage Transconductance Amplifier (VDVTA). All the above active elements were also designed in CMOS bulk-driven technology for LP LV applications. This thesis is also focused on replacement of conventional inductors by synthetic ones in passive LC ladder filters. These replacements can lead to the synthesis of active filters with interesting parameters.

Very large time constant Gm-C Filters

In this study a set of tools for the design of fully integrated transconductor-capacitor (Gm-C) filters, with very large time constants and current consumption under one micro-Ampere are presented. The selected application is a 2nd order bandpass-filter-amplifier, with a gain of 400 from 0.5 to 7Hz, carrying out the signal conditioning of a piezoelectric accelerometer which is part of an implantable cardiac pacemaker. The main challenge is to achieve very large time constants, without using any discrete external component. The chosen circuit technique to fulfill the requirement is series-parallel current division applied to standard symmetrical transconductors (OTAs). These circuits have demonstrated to be an excellent solution regarding their occupied area, power consumption, noise, linearity, and particularly offset. OTAs as low as 33pS -equivalent to a 30G resistor-, with up to 1V linear range, and input referred offset of a few mV, were designed, fabricated in a standard 0.8 micron CMOS technology, and tested. The application requires the series-parallel association of a large number of transistors, and the use of bias currents as low as a few pico-Amperes, which is not very common in analog integrated circuits. In this case the designer should employ maximum care in the selection of the transistor models to be used. A central aspect of this thesis was also to evaluate and develop noise and offset estimation models which was not obvious in the very beginning of the research. In the first two chapters an introduction to the target application is presented, and several MOS transistor characteristics in terms of the inversion coefficient -using the ACM transistor model- are evaluated. In chapter 3 it is discussed whether the usual flicker and thermal noise models are consistent regarding series-parallel association, and adequately represent the expected noise behavior under different bias conditions. A consistent, physics-based, one-equation-all-regions model for flicker noise in the MOS transistor is then presented. Several noise measurements are included demonstrating that the new model accurately fits widely different bias situations. A new model for mismatch offset in MOS transistors is presented, as a corollary of the flicker noise analysis. Finally, the correlation between flicker noise and mismatch offset, that can be seen as a DC noise, is shown. In chapter 4, the design of OTAs with an extended linear range, and very low transconductance, using series-parallel current division is presented. Precise tools are introduced for the estimation of noise and mismatch offset in series-parallel current mirrors, that are shown to help in the reduction of inaccuracies in the copy of currents with a large copy factor. The design and measurement of several OTA examples are presented. In chapter 5, the developed tools, and the OTAs shown, are employed in the design of the above mentioned filter for the piezoelectric accelerometer. A general methodology for the design of Gm-C filters with similar characteristics is established. The filter was fabricated and tested, successfully operating with a total power consumption of 233nA, up to a 2V power supply, with an input noise and mismatch offset of 2-4 Vrms, and 18 V respectively. To summarize the main results obtained were: The development of a new flicker noise model, the study of the effect of mismatch regarding series-parallel association, a new design methodology for OTAs and Gm-C filters. It is our hope that this constitutes a helpful set of tools for the circuit designer.En esta tesis se presenta un conjunto de herramientas para el diseño de circuitos integrados que implementan filtros transconductor-capacitor (Gm-C), de muy altas constantes de tiempo, con bajo ruido, y consumo de corriente por debajo del micro-Ampere. Como ejemplo de aplicación se toma un amplificador-pasabanda 2º orden, de ganancia 400 en la banda de 0.5 a 7Hz, que realiza el acondicionamiento de señal de un acelerómetro piezoeléctrico a ser empleado en un marcapasos implantable. El principal desafío es realizar en dicho filtro de tiempo continuo, muy altas constantes de tiempo sin usar componentes externos. La técnica elegida para alcanzar tal objetivo es la división serie-paralelo de corriente en transconductores (OTAs) simétricos estándar. Estos circuitos demostraron ser una excelente solución en cuanto al área ocupada, su consumo, ruido, linealidad, y en particular offset. Se diseñaron, fabricaron, y midieron, OTAs hasta 33pS -equivalente a una resistencia de 30G -, con hasta 1V de rango de lineal, y offset a la entrada de algunos mV, utilizando una tecnología CMOS de 0.8 micras de largo mínimo de canal. La aplicación requiere la asociación serie-paralelo de un gran número de transistores, y polarización con corrientes de hasta pico-Amperes, lo que constituye una situación poco frecuente en circuitos integrados analógicos. En este marco el diseñador debe elegir los modelos de transistor con sumo cuidado. Un aspecto central de esta tesis es también, el estudio y presentación de modelos adecuados de ruido y offset, que no resultan obvios al principio. En los primeros dos capítulos se realiza una introducción y se revisa, utilizando el modelo ACM, diferentes características del transistor MOS en función del nivel de inversión. En el capítulo 3 revisa la pertinencia y consistencia frente a la asociación serie-paralelo, de los modelos usuales de ruido de flicker o 1/f, y térmico. Luego se presenta, incluyendo medidas, un nuevo modelo físico, consistente, simple, y válido en todas las regiones de operación del transistor MOS, para el ruido de flicker. Como corolario a este estudio se presenta un nuevo modelo para estimar el desapareo entre transistores, en función no solo de la geometría, pero también de la polarización. Se demuestra la correlación, debido a su origen físico análogo, entre el ruido de flicker y el offset por desapareo que puede ser visto como un ruido en DC. En el capítulo 4 se presenta el diseño de OTAs con rango de linealidad extendido, y muy baja transconductancia, utilizando división serie-paralelo de corriente. Se presentan herramientas precisas para la estimación de offset y ruido y se demuestra la utilidad de la técnica para reducir el offset en espejos de corriente. Se presenta el diseño y medida de diversos OTAs. En el capítulo 5, las herramientas desarrolladas, y los OTAs presentados, son empleados en el diseño del filtro descripto para un acelerómetro piezoeléctrico. Se establece una metodología general para el diseño de filtros Gm-C con características similares. El filtro se fabricó y midió, operando en forma satisfactoria, con un consumo total de 230nA y hasta los 2V de tensión de alimentación, con ruido y offset a la entrada de tan solo 2-4 Vrms, y 18 V respectivamente. El desarrollo de un nuevo modelo de ruido 1/f para el transistor MOS, el estudio de la influencia del offset frente a la asociación serie-paralelo y su aplicación en OTAs, la metodología de diseño empleada, la demostración del uso de técnicas novedosas en una aplicación como la elegida que tiene relevancia tecnológica e interés académico; esperamos que todo ello constituya una contribución valiosa para la comunidad científica en microelectrónica y un conjunto de herramientas de utilidad para el diseño de circuitos

Design of Second Order Low Pass and High Pass Filter using Double Gate MOSFET based OTA

OTA-C filters are one of the most widely used as continuous time filters. It is because they are fast active integrators, provides low-power operation and tuning of the filter characteristics at higher frequencies. At high frequencies, the OP AMP based active filters has limited performance. We cannot change the values of resistors and inductors but OTA-C filter provides ability to change their values by changing the transconductance of OTA. Second order low and high pass filter structures have widespread applications. The double gate MOSFETs show better performance in the nanometer range of operation. Because it has better control over short channel effects (SCE’s) and other scaling related problems like gate leakage, sub-threshold conduction. Double gate MOSFET is four terminal device and back gate can be used for biasing which can tune the characteristics of circuit. This will provide additional advantage of low power and reduced area. This paper presents second order low pass and high pass filter based on double gate OTA for VHF and UHF frequency applications. The proposed filter consists of two OTAs and two capacitors. This filter shows low sensitivity to passive components, low component count and ease in design.  The simulation results shows pass band frequency of 14MHz and power consumption of 153.4 µwatt. The simulations are done using Tanner EDA version 13.0 at 90nm technology. Keywords: DG MOSFETs; OTA-C; Analog tunable circuits; Gain; Bandwidth; Double gate; Self cascode technique; Low pass filter; High pass filter

Ultra Low Power Amplification and Digitization System for Neural Signal Recording Applications

The scope is to develop a tunable low power fully integrated bandpass filter and a low power second order sigma-delta ADC modulator for implantable neural signal amplification and digitization applications, with subthreshold circuit design techniques in different CMOS processes. Since biopotentials usually contain low frequency components, the neural filters in this project have to be able to achieve large and predictable time constant for implantable applications. Voltage biased pseudo-resistors are vulnerable to process variations and circuit imperfections, and hence not suitable for implantable applications. A current biased pseudo-resistor is implemented in the neural filters in this work to set the cutoff frequency, and a Taylor series is used to study its linearity. The filters with proposed current biased pseudo-resistors were fabricated in two different CMOS processes and tested. The test results verify that the filters with current biased pseudo-resistors are tunable, and not vulnerable to process variations and circuit imperfections. The filters with current biased pseudo-resistors meet the design requirements of fully integrated, implantable applications. The sigma-delta ADC modulator was designed and simulated in a half micron SOS CMOS process. The simulation results of the ADC confirm the possibility of an ultra low power ADC for neural signal recording applications.School of Electrical & Computer Engineerin

0.3-Volt Rail-to-Rail DDTA and Its Application in a Universal Filter and Quadrature Oscillator

This paper presents the extremely low-voltage supply of the CMOS structure of a differential difference transconductance amplifier (DDTA). With a 0.3-volt supply voltage, the circuit offers rail-to-rail operational capability. The circuit is designed for low-frequency biomedical and sensor applications, and it consumes 357.4 nW of power. Based on two DDTAs and two grounded capacitors, a voltage-mode universal filter and quadrature oscillator are presented as applications. The universal filter possesses high-input impedance and electronic tuning ability of the natural frequency in the range of tens up to hundreds of Hz. The total harmonic distortion (THD) for the band-pass filter was 0.5% for 100 mV(pp) @ 84.47 Hz input voltage. The slight modification of the filter yields a quadrature oscillator. The condition and the frequency of oscillation are orthogonally controllable. The frequency of oscillation can also be controlled electronically. The THD for a 67 Hz oscillation frequency was around 1.2%. The circuit is designed and simulated in a Cadence environment using 130 nm CMOS technology from United Microelectronics Corporation (UMC). The simulation results confirm the performance of the designed circuits