Transistor-Level Synthesis of Pipeline Analog-to-Digital Converters Using a Design-Space Reduction Algorithm

A novel transistor-level synthesis procedure for pipeline ADCs is presented. This procedure is able to directly map high-level converter specifications onto transistor sizes and biasing conditions. It is based on the combination of behavioral models for performance evaluation, optimization routines to minimize the power and area consumption of the circuit solution, and an algorithm to efficiently constraint the converter design space. This algorithm precludes the cost of lengthy bottom-up verifications and speeds up the synthesis task. The approach is herein demonstrated via the design of a 0.13 μm CMOS 10 bits@60 MS/s pipeline ADC with energy consumption per conversion of only 0.54 pJ@1 MHz, making it one of the most energy-efficient 10-bit video-rate pipeline ADCs reported to date. The computational cost of this design is of only 25 min of CPU time, and includes the evaluation of 13 different pipeline architectures potentially feasible for the targeted specifications. The optimum design derived from the synthesis procedure has been fine tuned to support PVT variations, laid out together with other auxiliary blocks, and fabricated. The experimental results show a power consumption of 23 [email protected] V and an effective resolution of 9.47-bit@1 MHz. Bearing in mind that no specific power reduction strategy has been applied; the mentioned results confirm the reliability of the proposed approach.Ministerio de Ciencia e Innovación TEC2009-08447Junta de Andalucía TIC-0281

Coulomb blockade in a Si channel gated by an Al single-electron transistor

We incorporate an Al-AlO_x-Al single-electron transistor as the gate of a narrow (~100 nm) metal-oxide-semiconductor field-effect transistor (MOSFET). Near the MOSFET channel conductance threshold, we observe oscillations in the conductance associated with Coulomb blockade in the channel, revealing the formation of a Si single-electron transistor. Abrupt steps present in sweeps of the Al transistor conductance versus gate voltage are correlated with single-electron charging events in the Si transistor, and vice versa. Analysis of these correlations using a simple electrostatic model demonstrates that the two single-electron transistor islands are closely aligned, with an inter-island capacitance approximately equal to 1/3 of the total capacitance of the Si transistor island, indicating that the Si transistor is strongly coupled to the Al transistor.Comment: 3 pages, 4 figures, 1 table; typos corrected, minor clarifications added; published in AP

Table 1. Typical performance RF performance at Tcase = 25 �C in a class-AB production test circuit. Mode of operation f VDS PL(AV) Gp �D ACPR885k ACPR1980k

[1] Single carrier N-CDMA with pilot, paging sync and 6 traffic channels (Walsh codes 8- 13). PAR = 9.7 dB at 0.01 % probability on CCDF. Channel bandwidth is 1.23 MHz. [2] Measured within 30 kHz bandwidth. CAUTION This device is sensitive to ElectroStatic Discharge (ESD). Therefore care should be taken during transport and handling. 1.2 Features and benefit

Voltage regulator for battery power source

A bipolar transistor in series with the battery as the control element also in series with a zener diode and a resistor is used to maintain a predetermined voltage until the battery voltage decays to very nearly the predetermined voltage. A field effect transistor between the base of the bipolar transistor and a junction between the zener diode and resistor regulates base current of the bipolar transistor, thereby regulating the conductivity of the bipolar transistor for control of the output voltage

Magnetic bipolar transistor

A magnetic bipolar transistor is a bipolar junction transistor with one or more magnetic regions, and/or with an externally injected nonequilibrium (source) spin. It is shown that electrical spin injection through the transistor is possible in the forward active regime. It is predicted that the current amplification of the transistor can be tuned by spin.Comment: 4 pages, 2 figure

Critical Evaluation of Organic Thin-Film Transistor Models

Thin-film transistors (TFTs) represent a wide-spread tool to determine the charge-carrier mobility of materials. Mobilities and further transistor parameters like contact resistances are commonly extracted from the electrical characteristics. However, the trust in such extracted parameters is limited, because their values depend on the extraction technique and on the underlying transistor model. We propose a technique to establish whether a chosen model is adequate to represent the transistor operation. This two-step technique analyzes the electrical measurements of a series of TFTs with different channel lengths. The first step extracts the parameters for each individual transistor by fitting the full output and transfer characteristics to the transistor model. The second step checks whether the channel-length dependence of the extracted parameters is consistent with the model. We demonstrate the merit of the technique for distinct sets of organic TFTs that differ in the semiconductor, the contacts, and the geometry. Independent of the transistor set, our technique consistently reveals that state-of-the-art transistor models fail to reproduce the correct channel-length dependence. Our technique suggests that contemporary transistor models require improvements in terms of charge-carrier-density dependence of the mobility and/or the consideration of uncompensated charges in the transistor channel.Comment: 20 pages, 10 figure

Improved chopper circuit uses parallel transistors

Parallel transistor chopper circuit operates with one transistor in the forward mode and the other in the inverse mode. By using this method, it acts as a single, symmetrical, bidirectional transistor, and reduces and stabilizes the offset voltage

Hybrid power semiconductor

The voltage rating of a bipolar transistor may be greatly extended while at the same time reducing its switching time by operating it in conjunction with FETs in a hybrid circuit. One FET is used to drive the bipolar transistor while the other FET is connected in series with the transistor and an inductive load. Both FETs are turned on or off by a single drive signal of load power, the second FET upon ceasing conductions, rendering one power electrode of the bipolar transistor open. Means are provided to dissipate currents which flow after the bipolar transistor is rendered nonconducting

An algorithm for transistor sizing in CMOS circuits

This paper describes a novel algorithm for automatic transistor sizing which is one technique for improving timing performance in CMOS circuits. The sizing algorithm is used to minimize area and power subject to timing constraints. We define the transistor sizing problem as a graph problem and use a non-linear optimization technique. The algorithm consists of three separate tasks: critical path analysis, transistor sizing and transistor desizing. The main contribution of the presented algorithm is that the delays of all paths in a given design can be tuned simultaneously to satisfy timing constraints. Furthermore, the minimal transistor area and minimal power dissipation under giving timing constraints can be achieved. Experimental results show that this approach has greater control over area/time tradeoffs than traditional sizing algorithms

A one-transistor-synapse strategy for electrically-programmable massively-parallel analog array processors

This paper presents a linear, four-quadrants, electrically-programmable, one-transistor synapse strategy applicable to the implementation of general massively-parallel analog processors in CMOS technology. It is specially suited for translationally-invariant processing arrays with local connectivity, and results in a significant reduction in area occupation and power dissipation of the basic processing units. This allows higher integration densities and therefore, permits the integration of larger arrays on a single chip.Comisión Interministerial de Ciencia y Tecnología TIC96- 1392-C02-0