This paper describes a novel algorithm for automatic transistor sizing which is one technique for improving timing performance in CMOS circuits. The sizing algorithm is used to minimize area and power subject to timing constraints. We define the transistor sizing problem as a graph problem and use a non-linear optimization technique. The algorithm consists of three separate tasks: critical path analysis, transistor sizing and transistor desizing. The main contribution of the presented algorithm is that the delays of all paths in a given design can be tuned simultaneously to satisfy timing constraints. Furthermore, the minimal transistor area and minimal power dissipation under giving timing constraints can be achieved. Experimental results show that this approach has greater control over area/time tradeoffs than traditional sizing algorithms
