11 research outputs found
Reduced pin-count testing, 3D SICs, time division multiplexing, test access mechanism, simultaneous bidirectional signaling
3D Stacked Integrated Circuits (SICs) offer a promising way to cope with the technology scaling; however, the test access requirements are highly complicated due to increased transistor density and a limited number of test channels. Moreover, although the vertical interconnects in 3D SIC are capable of high-speed data transfer, the overall test speed is restricted by scan-chains that are not optimized for timing. Reduced Pin-Count Testing (RPCT) has been effectively used under these scenarios. In particular, Time Division Multiplexing (TDM) allows full utilization of interconnect bandwidth while providing low scan frequencies supported by the scan chains. However, these methods rely on Uni-Directional Signaling (UDS), in which a chip terminal (pin or a TSV) can either be used to transmit or receive data at a given time. This requires that at least two chip terminals are available at every die interface (Tester-Die or Die-Die) to form a single test channel. In this paper, we propose Simultaneous Bi-Directional Signaling (SBS), which allows a chip terminal to be used simultaneously to send and receive data, thus forming a test channel using one pin instead of two. We demonstrate how SBS can be used in conjunction with TDM to achieve reduced pin count testing while using only half the number of pins compared to conventional TDM based methods, consuming only 22.6% additional power. Alternatively, the advantage could be manifested as a test time reduction by utilizing all available test channels, allowing more parallelism and test time reduction down to half compared to UDS-based TDM. Experiments using 45nm technology suggest that the proposed method can operate at up to 1.2 GHz test clock for a stack of 3-dies, whereas for higher frequencies, a binary-weighted transmitter is proposed capable of up to 2.46 GHz test clock
์ฐจ์ธ๋ ์๋์ฐจ์ฉ ์นด๋ฉ๋ผ ๋ฐ์ดํฐ ํต์ ์ ์ํ ๋น๋์นญ ๋์ ์๋ฐฉํฅ ์ก์์ ๊ธฐ์ ์ค๊ณ
ํ์๋
ผ๋ฌธ(๋ฐ์ฌ) -- ์์ธ๋ํ๊ต๋ํ์ : ๊ณต๊ณผ๋ํ ์ ๊ธฐยท์ ๋ณด๊ณตํ๋ถ, 2022.2. ์ ๋๊ท .๋ณธ ํ์ ๋
ผ๋ฌธ์์๋ ์ฐจ์ธ๋ ์๋์ฐจ์ฉ ์นด๋ฉ๋ผ ๋งํฌ๋ฅผ ์ํด ๋์ ์๋์ 4๋ ๋ฒจ ํ์ค ์งํญ ๋ณ์กฐ ์ ํธ์ ๋ฎ์ ์๋์ 2๋ ๋ฒจ ํ์ค ์งํญ ๋ณ์กฐ ์ ํธ๋ฅผ ํต์ ํ๋ ๋น๋์นญ ๋์ ์๋ฐฉํฅ ์ก์์ ๊ธฐ์ ์ค๊ณ ๊ธฐ์ ์ ๋ํด ์ ์ํ๊ณ ๊ฒ์ฆ๋์๋ค.
์ฒซ๋ฒ์งธ ํ๋กํ ํ์
์ค๊ณ์์๋, 10B6Q ์ง๋ฅ ๋ฐธ๋ฐ์ค ์ฝ๋๋ฅผ ํ์ฌํ 4๋ ๋ฒจ ํ์ค ์งํญ ๋ณ์กฐ ์ก์ ๊ธฐ์ ๊ณ ์ ๋ ๋ฐ์ดํฐ์ ์ฐธ์กฐ ๋ ๋ฒจ์ ๊ฐ์ง๋ 4๋ ๋ฒจ ํ์ค ์งํญ ๋ณ์กฐ ์ ์ํ ์์ ๊ธฐ์ ๋ํ ๋ด์ฉ์ด ๊ธฐ์ ๋์๋ค. 4๋ ๋ฒจ ํ์ค ์งํญ ๋ณ์กฐ ์ก์ ๊ธฐ์์๋ ๊ต๋ฅ ์ฐ๊ฒฐ ๋งํฌ ์์คํ
์ ๋์ํ๊ธฐ ์ํ ๋ฉด์ ๋ฐ ์ ๋ ฅ ํจ์จ์ฑ์ด ์ข์ 10B6Q ์ฝ๋๊ฐ ์ ์๋์๋ค. ์ด ์ฝ๋๋ ์ง๋ฅ ๋ฐธ๋ฐ์ค๋ฅผ ๋ง์ถ๊ณ ์ฐ์์ ์ผ๋ก ๊ฐ์ ์ฌ๋ณผ์ ๊ฐ์ง๋ ๊ธธ์ด๋ฅผ 6๊ฐ๋ก ์ ํ ์ํจ๋ค. ๋น๋ก ์ฌ๊ธฐ์๋ ์
๋ ฅ ๋ฐ์ดํฐ ๊ธธ์ด 10๋นํธ๋ฅผ ์ฌ์ฉํ์์ง๋ง, ์ ์๋ ๊ธฐ์ ์ ์นด๋ฉ๋ผ์ ๋ค์ํ ๋ฐ์ดํฐ ํ์
์ ๋์ํ ์ ์๋๋ก ์
๋ ฅ ๋ฐ์ดํฐ ๊ธธ์ด์ ๋ํ ํ์ฅ์ฑ์ ๊ฐ์ง๋ค. ๋ฐ๋ฉด, 4๋ ๋ฒจ ํ์ค ์งํญ ๋ณ์กฐ ์ ์ํ ์์ ๊ธฐ์์๋, ์ํ๋ฌ์ ์ต์
์ ์ต์ ์ผ๋ก ์ ๊ฑฐํ์ฌ ๋ ๋ฎ์ ๋นํธ์๋ฌ์จ์ ์ป๊ธฐ ์ํด์, ๊ธฐ์กด์ ๋ฐ์ดํฐ ๋ฐ ์ฐธ์กฐ ๋ ๋ฒจ์ ์กฐ์ ํ๋ ๋์ , ์ด ๋ ๋ฒจ๋ค์ ๊ณ ์ ์ํค๊ณ ๊ฐ๋ณ ๊ฒ์ธ ์ฆํญ๊ธฐ๋ฅผ ์ ์ํ์ผ๋ก ์กฐ์ ํ๋๋ก ํ์๋ค. ์๊ธฐ 10B6Q ์ฝ๋ ๋ฐ ๊ณ ์ ๋ฐ์ดํฐ ๋ฐ ์ฐธ์กฐ๋ ๋ฒจ ๊ธฐ์ ์ ๊ฐ์ง ํ๋กํ ํ์
์นฉ๋ค์ 40 ๋๋
ธ๋ฏธํฐ ์ํธ๋ณด์ํ ๋ฉํ ์ฐํ ๋ฐ๋์ฒด ๊ณต์ ์ผ๋ก ์ ์๋์๊ณ ์นฉ ์จ ๋ณด๋ ํํ๋ก ํ๊ฐ๋์๋ค. 10B6Q ์ฝ๋๋ ํฉ์ฑ ๊ฒ์ดํธ ์ซ์๋ 645๊ฐ์ ํจ๊ป ๋จ 0.0009 mm2 ์ ๋ฉด์ ๋ง์ ์ฐจ์งํ๋ค. ๋ํ, 667 MHz ๋์ ์ฃผํ์์์ ๋จ 0.23 mW ์ ์ ๋ ฅ์ ์๋ชจํ๋ค. 10B6Q ์ฝ๋๋ฅผ ํ์ฌํ ์ก์ ๊ธฐ์์ 8-Gb/s 4๋ ๋ฒจ ํ์ค ์งํญ ๋ณ์กฐ ์ ํธ๋ฅผ ๊ณ ์ ๋ฐ์ดํฐ ๋ฐ ์ฐธ์กฐ ๋ ๋ฒจ์ ๊ฐ์ง๋ ์ ์ํ ์์ ๊ธฐ๋ก 12-m ์ผ์ด๋ธ (22-dB ์ฑ๋ ๋ก์ค) ์ ํตํด์ ๋ณด๋ธ ๊ฒฐ๊ณผ ์ต์ ๋นํธ ์๋ฌ์จ 108 ์ ๋ฌ์ฑํ์๊ณ , ๋นํธ ์๋ฌ์จ 105 ์์๋ ์์ด ๋ง์ง์ด 0.15 UI x 50 mV ๋ณด๋ค ํฌ๊ฒ ์ธก์ ๋์๋ค. ์ก์์ ๊ธฐ๋ฅผ ํฉ์น ์ ๋ ฅ ์๋ชจ๋ 65.2 mW (PLL ์ ์ธ) ์ด๊ณ , ์ฑ๊ณผ์ ๋ํ์์น๋ 0.37 pJ/b/dB ๋ฅผ ๋ณด์ฌ์ฃผ์๋ค.
์ฒซ๋ฒ์งธ ํ๋กํ ํ์
์ค๊ณ์ ํฌํจํ์ฌ ๊ฐ์ ๋ ๋๋ฒ์งธ ํ๋กํ ํ์
์ค๊ณ์์๋, 12-Gb/s 4๋ ๋ฒจ ํ์ค ์งํญ ๋ณ์กฐ ์ ๋ฐฉํฅ ์ฑ๋ ์ ํธ์ 125-Mb/s 2๋ ๋ฒจ ํ์ค ์งํญ ๋ณ์กฐ ์ญ๋ฐฉํฅ ์ฑ๋ ์ ํธ๋ฅผ ํ์ฌํ ๋น๋์นญ ๋์ ์๋ฐฉํฅ ์ก์์ ๊ธฐ์ ๋ํด ๊ธฐ์ ๋๊ณ ๊ฒ์ฆ๋์๋ค. ์ ์๋ ๋์ ์ ํ ๋ฒ์๋ฅผ ๊ฐ์ง๋ ํ์ด๋ธ๋ฆฌ๋๋ gmC ์ ๋์ญ ํต๊ณผ ํํฐ์ ์์ฝ ์ ๊ฑฐ๊ธฐ์ ํจ๊ป ์์๋ฐ์ด๋ ์ ํธ๋ฅผ 24 dB ์ด์ ํจ์จ์ ์ผ๋ก ๊ฐ์์์ผฐ๋ค. ๋ํ, ๋์ ์ ํ ๋ฒ์๋ฅผ ๊ฐ์ง๋ ํ์ด๋ธ๋ฆฌ๋์ ํจ๊ป ๊ฒ์ธ ๊ฐ์๊ธฐ๋ฅผ ํ์ฑํ๊ฒ ๋๋ ์ ํ ๋ฒ์ ์ฆํญ๊ธฐ๋ฅผ ํตํด 4๋ ๋ฒจ ํ์ค ์งํญ ๋ณ์กฐ ์ ํธ์ ์ ํ์ฑ๊ณผ ์งํญ์ ํธ๋ ์ด๋ ์คํ ๊ด๊ณ๋ฅผ ๊นจ๋ ๊ฒ์ด ๊ฐ๋ฅํ์๋ค. ๋์ ์๋ฐฉํฅ ์ก์์ ๊ธฐ ์นฉ์ 40 ๋๋
ธ๋ฏธํฐ ์ํธ๋ณด์ํ ๋ฉํ ์ฐํ ๋ฐ๋์ฒด ๊ณต์ ์ผ๋ก ์ ์๋์๋ค. ์๊ธฐ ์ค๊ณ ๊ธฐ์ ๋ค์ ์ด์ฉํ์ฌ, 4๋ ๋ฒจ ํ์ค ์งํญ ๋ณ์กฐ ๋ฐ 2๋ ๋ฒจ ํ์ค ์งํญ ๋ณ์กฐ ์ก์์ ๊ธฐ ๋ชจ๋ 5m ์ฑ๋ (์ฑ๋ ๋ก์ค 15.9 dB) ์์ 1E-12 ๋ณด๋ค ๋ฎ์ ๋นํธ ์๋ฌ์จ์ ๋ฌ์ฑํ์๊ณ , ์ด 78.4 mW ์ ์ ๋ ฅ ์๋ชจ๋ฅผ ๊ธฐ๋กํ์๋ค. ์ข
ํฉ์ ์ธ ์ก์์ ๊ธฐ๋ ์ฑ๊ณผ ๋ํ์งํ๋ก 0.41 pJ/b/dB ์ ํจ๊ป ๋์ ์๋ฐฉํฅ ํต์ ์๋์์ 4๋ ๋ฒจ ํ์ค ์งํญ ๋ณ์กฐ ์ ํธ ๋ฐ 2๋ ๋ฒจ ํ์ค ์งํญ ๋ณ์กฐ ์ ํธ ๊ฐ๊ฐ์์ ์์ด ๋ง์ง 0.15 UI ์ 0.57 UI ๋ฅผ ๋ฌ์ฑํ์๋ค. ์ด ์์น๋ ์ฑ๊ณผ ๋ํ์งํ 0.5 ์ดํ๋ฅผ ๊ฐ์ง๋ ๊ธฐ์กด ๋์ ์๋ฐฉํฅ ์ก์์ ๊ธฐ์์ ๋น๊ต์์ ์ต๊ณ ์ ์์ด ๋ง์ง์ ๊ธฐ๋กํ์๋ค.In this dissertation, design techniques of a highly asymmetric simultaneous bidirectional (SB) transceivers with high-speed PAM-4 and low-speed PAM-2 signals are proposed and demonstrated for the next-generation automotive camera link.
In a first prototype design, a PAM-4 transmitter with 10B6Q DC balance code and a PAM-4 adaptive receiver with fixed data and threshold levels (dtLevs) are presented. In PAM-4 transmitter, an area- and power-efficient 10B6Q code for an AC coupled link system that guarantees DC balance and limited run length of six is proposed. Although the input data width of 10 bits is used here, the proposed scheme has an extensibility for the input data width to cover various data types of the camera. On the other hand, in the PAM-4 adaptive receiver, to optimally cancel the sampler offset for a lower BER, instead of adjusting dtLevs, the gain of a programmable gain amplifier is adjusted adaptively under fixed dtLevs. The prototype chips including above proposed 10B6Q code and fixed dtLevs are fabricated in 40-nm CMOS technology and tested in chip-on-board assembly. The 10B6Q code only occupies an active area of 0.0009 mm2 with a synthesized gate count of 645. It also consumes 0.23 mW at the operating clock frequency of 667 MHz. The transmitter with 10B6Q code delivers 8-Gb/s PAM-4 signal to the adaptive receiver using fixed dtLevs through a lossy 12-m cable (22-dB channel loss) with a BER of 1E-8, and the eye margin larger than 0.15 UI x 50 mV is measured for a BER of 1E-5. The proto-type chips consume 65.2 mW (excluding PLL), exhibiting an FoM of 0.37 pJ/b/dB.
In a second prototype design advanced from the first prototypes, An asymmetric SB transceivers incorporating a 12-Gb/s PAM-4 forward channel and a 125-Mb/s PAM-2 back channel are presented and demonstrated. The proposed wide linear range (WLR) hybrid combined with a gmC low-pass filter and an echo canceller effectively suppresses the outbound signals by more than 24dB. In addition, linear range enhancer which forms a gain attenuator with WLR hybrid breaks the trade-off between the linearity and the amplitude of the PAM-4 signal. The SB transceiver chips are separately fabricated in 40-nm CMOS technology. Using above design techniques, both PAM-4 and PAM-2 SB transceivers achieve BER less than 1E-12 over a 5-m channel (15.9 dB channel loss), consuming 78.4 mW. The overall transceivers achieve an FoM of 0.41 pJ/b/dB and eye margin (at BER of 1E-12) of 0.15 UI and 0.57 UI for the forward PAM-4 and back PAM-2 signals, respectively, under SB communication. This is the best eye margin compared to the prior art SB transceivers with an FoM less than 0.5.CHAPTER 1 INTRODUCTION 1
1.1 MOTIVATION 1
1.2 DISSERTATION ORGANIZATION 4
CHAPTER 2 BACKGROUND ON AUTOMOTIVE CAMERA LINK 6
2.1 OVERVIEW 6
2.2 SYSTEM REQUIREMENTS 10
2.2.1 CHANNEL 10
2.2.2 POWER OVER DIFFERENTIAL LINE (PODL) 12
2.2.3 AC COUPLING AND DC BALANCE CODE 15
2.2.4 SIMULTANEOUS BIDIRECTIONAL COMMUNICATION 18
2.2.4.1 HYBRID 18
2.2.4.2 ECHO CANCELLER 20
2.2.5 ADAPTIVE RECEIVE EQUALIZATION 22
CHAPTER 3 AREA AND POWER EFFICIENT 10B6Q ENCODER FOR DC BALANCE 25
3.1 INTRODUCTION 25
3.2 PRIOR WORKS 28
3.3 PROPOSED AREA- AND POWER-EFFICIENT 10B6Q PAM-4 CODER 30
3.4 DESIGN OF THE 10B6Q CODE 33
3.4.1 PAM-4 DC BALANCE 35
3.4.2 PAM-4 TRANSITION DENSITY 35
3.4.3 10B6Q DECODER 37
3.5 IMPLEMENTATION AND MEASUREMENT RESULTS 40
CHAPTER 4 PAM-4 TRANSMITTER AND ADAPTIVE RECEIVER WITH FIXED DATA AND THRESHOLD LEVELS 45
4.1 INTRODUCTION 45
4.2 PRIOR WORKS 47
4.3 ARCHITECTURE AND IMPLEMENTATION 49
4.2.1 PAM-4 TRANSMITTER 49
4.2.2 PAM-4 ADAPTIVE RECEIVER 52
4.3 MEASUREMENT RESULTS 62
CHAPTER 5 ASYMMETRIC SIMULTANEOUS BIDIRECTIONAL TRANSCEIVERS USING WIDE LINEAR RANGE HYBRID 68
5.1 INTRODUCTION 68
5.2 PRIOR WORKS 70
5.3 WIDE LINEAR RANGE (WLR) HYBRID 75
5.3 IMPLEMENTATION 78
5.3.1 SERIALIZER (SER) DESIGN 78
5.3.2 DESERIALIZER (DES) DESIGN 79
5.4 HALF CIRCUIT ANALYSIS OF WLR HYBRID AND LRE 82
5.5 MEASUREMENT RESULTS 88
CHAPTER 6 CONCLUSION 97
BIBLIOGRAPHY 99
์ด ๋ก 106๋ฐ
Integrating simultaneous bi-direction signalling in the test fabric of 3D stacked integrated circuits.
Jennions, Ian K. - Associate SupervisorThe world has seen significant advancements in electronic devicesโ capabilities,
most notably the ability to embed ultra-large-scale functionalities in lightweight,
area and power-efficient devices. There has been an enormous push towards
quality and reliability in consumer electronics that have become an indispensable
part of human life. Consequently, the tests conducted on these devices at the
final stages before these are shipped out to the customers have a very high
significance in the research community. However, researchers have always
struggled to find a balance between the test time (hence the test cost) and the
test overheads; unfortunately, these two are inversely proportional.
On the other hand, the ever-increasing demand for more powerful and compact
devices is now facing a new challenge. Historically, with the advancements in
manufacturing technology, electronic devices witnessed miniaturizing at an
exponential pace, as predicted by Mooreโs law. However, further geometric or
effective 2D scaling seems complicated due to performance and power concerns
with smaller technology nodes. One promising way forward is by forming 3D
Stacked Integrated Circuits (SICs), in which the individual dies are stacked
vertically and interconnected using Through Silicon Vias (TSVs) before being
packaged as a single chip. This allows more functionality to be embedded with a
reduced footprint and addresses another critical problem being observed in 2D
designs: increasingly long interconnects and latency issues. However, as more
and more functionality is embedded into a small area, it becomes increasingly
challenging to access the internal states (to observe or control) after the device
is fabricated, which is essential for testing. This access is restricted by the limited
number of Chip Terminals (IC pins and the vertical Through Silicon Vias) that a
chip could be fitted with, the power consumption concerns, and the chip area
overheads that could be allocated for testing.
This research investigates Simultaneous Bi-Directional Signaling (SBS) for use
in Test Access Mechanism (TAM) designs in 3D SICs. SBS enables chip
terminals to simultaneously send and receive test vectors on a single Chip
Terminal (CT), effectively doubling the per-pin efficiency, which could be
translated into additional test channels for test time reduction or Chip Terminal
reduction for resource efficiency. The research shows that SBS-based test
access methods have significant potential in reducing test times and/or test
resources compared to traditional approaches, thereby opening up new avenues
towards cost-effectiveness and reliability of future electronics.PhD in Manufacturin
The 7TM-independent (trans) function of the Adhesion GPCR Latrophilin-1 in C. elegans neuron morphogenesis and germ cell proliferation: Thesis submitted for the degree of Dr. med.
In meiner Dissertation klรคrte ich wesentliche Fragen zu 7-Transmembrandomรคnen-unabhรคngigen Funktionen von Adhรคsions-G-protein-gekoppelten Rezeptoren auf. Diese einzigartigen Zelloberflรคchenmolekรผle sind essentiell fรผr die Physiologie des Menschen, jedoch auf molekularer Ebene erst in Grundzรผgen verstanden. Unter anderem haben sie als G-protein-gekoppelte Rezeptoren die Fรคhigkeit, Signale aus der zellulรคren Umgebung mittels ihrer 7-Transmembrandomรคne in die Zelle weiterzuleiten. Jedoch sind sie auch im Stande unabhรคngig von ihrer 7-Transmembrandomรคne agieren. In meiner Arbeit zeigte ich wie solche Funktionen in vivo implementiert werden kรถnnen und prรคsentierte weiterhin, dass die Rezeptoren in diesem Kontext entgegen ihrer 'Natur' im Stande sind, Signale auf benachbarten Zellen auszulรถsen. Meine Arbeit bildet somit die Grundlage zur weiteren Erforschung der komplexen Signalmechanismen von Adhรคsions-GPCRs
Design Techniques for High Pin Efficiency Wireline Transceivers
While the majority of wireline research investigates bandwidth improvement and how to overcome the high channel loss, pin efficiency is also critical in high-performance wireline applications. This dissertation proposes two different implementations for high pin efficiency wireline transceivers. The first prototype achieves twice pin efficiency than unidirectional signaling, which is 32Gb/s simultaneous bidirectional transceiver supporting transmission and reception on the same channel at the same time. It includes an efficient low-swing voltage-mode driver with an R-gm hybrid for signal separation, combining the continuous-time-linear-equalizer (CTLE) and echo cancellation (EC) in a single stage, and employing a low-complexity 5/4X CDA system. Support of a wide range of channels is possible with foreground adaptation of the EC finite impulse response (FIR) filter taps with a sign-sign least-mean-square (SSLMS) algorithm. Fabricated in TSMC 28-nm CMOS, the 32Gb/s SBD transceiver occupies area and achieves 16Gb/s uni-directional and 32Gb/s simultaneous bi-directional signals. 32Gb/s SBD operation consumes 1.83mW/Gb/s with 10.8dB channel loss at Nyquist rate. The second prototype presents an optical transmitter with a quantum-dot (QD) microring laser. This can support wavelength-division multiplexing allowing for high pin efficiency application by packing multiple high-bandwidth signals onto one optical channel. The development QD microring laser model accurately captures the intrinsic photonic high-speed dynamics and allows for the future co-design of the circuits and photonic device. To achieve higher bandwidth than intrinsic one, utilizing both techniques of optical injection locking (OIL) and 2-tap asymmetric Feed-forward equalizer (FFE) can perform 22Gb/s operation with 3.2mW/Gb/s. The first hybrid-integration directly-modulated OIL QD microring laser system is demonstrated
Clocking and Skew-Optimization For Source-Synchronous Simultaneous Bidirectional Links
There is continuous expansion of computing capabilities in mobile devices which
demands higher I/O bandwidth and dense parallel links supporting higher data rates. Highspeed
signaling leverages technology advancements to achieve higher data rates but is limited
by the bandwidth of the electrical copper channel which have not scaled accordingly.
To meet the continuous data-rate demand, Simultaneous Bi-directional (SBD) signaling
technique is an attractive alternative relative to uni-directional signaling as it can work at
lower clock speeds, exhibits better spectral efficiency and provides higher throughput in
pad limited PCBs.
For low-power and more robust system, the SBD transceiver should utilize forwarded
clock system and per-pin de-skew circuits to correct the phase difference developed
between the data and clock. The system can be configured in two roles, master and
slave. To save more power, the system should have only one clock generator. The master
has its own clock source and shares its clock to the slave through the clock channel, and the
slave uses this forwarded clock to deserialize the inbound data and serialize the outbound
data. A clock-to-data skew exists which can be corrected with a phase tracking CDR. This
thesis presents a low-power implementation of forwarded clocking and clock-to-data skew
optimization for a 40 Gbps SBD transceiver. The design is implemented in 28nm CMOS
technology and consumes 8.8mW of power for 20 Gbps NRZ data at 0.9 V supply. The
area occupied by the clocking 0.018 mm^2 area
High-speed, low cost test platform using FPGA technology
The object of this research is to develop a low-cost, adaptable testing platform for multi-GHz digital applications, with concentration on the test requirement of advanced devices. Since most advanced ATEs are very expensive, this equipment is not always available for testing cost-sensitive devices. The approach is to use recently-introduced advanced FPGAs for the core logic of the testing platform, thereby allowing for a low-cost, low power-consumption, high-performance, and adaptable test system. Furthermore to customize the testing system for specific applications, we implemented multiple extension testing modules base on this platform. With these extension modules, new functions can be added easily and the test system can be upgraded with specific features required for other testing purposes. The applications of this platform can help those digital devices to be delivered into market with shorter time, lower cost and help the development of the whole industry.Ph.D
2-wire time independent asynchronous communications
Communications both to and between low end microprocessors represents a real cost in a number of industrial and consumer products. This thesis starts by examining the properties of protocols that help to minimize these expenses and comes to the conclusion that the derived set of properties define a new category of communications protocol : Time Independent Asynchronous ( TIA) communications. To show the utility of the TIA category we develop a novel TIA protocol that uses only 2-wires and general IO pins on each host. The protocol is analyzed using the Petri net based STG ( Signal Transition Graph) which is widely use to model asynchronous logic. It is shown that STGs do not accurately model the behavior of software driven systems and so a modified form called STG-FT ( STG For Threads) is developed to better model software systems. A simulator is created to take an STG-FT model and perform a full reachability tree analysis to prove correctness and analyze livelock and deadlock properties. The simulator can also examine the full reachability tree for every possible system state ( the cross product of all sub-system states), and analyze deadlock and livelock issues related to unexpected inputs and unusual situations. Reachability pruning algorithms are developed which decrease the search tree by a factor of approximately 250 million. The 2-wire protocol is implemented between a PC and an Atmel Tiny26 microprocessor, there is also a variant that works between microprocessors. Testing verifies the simulation results including an avoidable livelock condition with data throughput peaking at a useful 50 kilobits/second in both directions. The first practical application of 2-wire TIA is part of a novel debugger for the Atmel Tiny26 microprocessor. The approach can be extended to any microprocessor with general IO pins. TIA communications, developed in this thesis, is a serious contender whenever low end microprocessors must communicate with other processors. Consumer and industrial products may be able to achieve cost saving by using this new protocol
Hybrid NRZ/Multi-Tone Signaling for High-Speed Low-Power Wireline Transceivers
Over the past few decades, incessant growth of Internet networking traffic and High-Performance Computing (HPC) has led to a tremendous demand for data bandwidth. Digital communication technologies combined with advanced integrated circuit scaling trends have enabled the semiconductor and microelectronic industry to dramatically scale the bandwidth of high-loss interfaces such as Ethernet, backplane, and Digital Subscriber Line (DSL). The key to achieving higher bandwidth is to employ equalization technique to compensate the channel impairments such as Inter-Symbol Interference (ISI), crosstalk, and environmental noise. Therefore, todayรขs advanced input/outputs (I/Os) has been equipped with sophisticated equalization techniques to push beyond the uncompensated bandwidth of the system. To this end, process scaling has continually increased the data processing capability and improved the I/O performance over the last 15 years. However, since the channel bandwidth has not scaled with the same pace, the required signal processing and equalization circuitry becomes more and more complicated. Thereby, the energy efficiency improvements are largely offset by the energy needed to compensate channel impairments. In this design paradigm, re-thinking about the design strategies in order to not only satisfy the bandwidth performance, but also to improve power-performance becomes an important necessity. It is well known in communication theory that coding and signaling schemes have the potential to provide superior performance over band-limited channels. However, the choice of the optimum data communication algorithm should be considered by accounting for the circuit level power-performance trade-offs. In this thesis we have investigated the application of new algorithm and signaling schemes in wireline communications, especially for communication between microprocessors, memories, and peripherals. A new hybrid NRZ/Multi-Tone (NRZ/MT) signaling method has been developed during the course of this research. The system-level and circuit-level analysis, design, and implementation of the proposed signaling method has been performed in the frame of this work, and the silicon measurement results have proved the efficiency and the robustness of the proposed signaling methodology for wireline interfaces. In the first part of this work, a 7.5 Gb/s hybrid NRZ/MT transceiver (TRX) for multi-drop bus (MDB) memory interfaces is designed and fabricated in 40 nm CMOS technology. Reducing the complexity of the equalization circuitry on the receiver (RX) side, the proposed architecture achieves 1 pJ/bit link efficiency for a MDB channel bearing 45 dB loss at 2.5 GHz. The measurement results of the first prototype confirm that NRZ/MT serial data TRX can offer an energy-efficient solution for MDB memory interfaces. Motivated by the satisfying results of the first prototype, in the second phase of this research we have exploited the properties of multi-tone signaling, especially orthogonality among different sub-bands, to reduce the effect of crosstalk in high-dense wireline interconnects. A four-channel transceiver has been implemented in a standard CMOS 40 nm technology in order to demonstrate the performance of NRZ/MT signaling in presence of high channel loss and strong crosstalk noise. The proposed system achieves 1 pJ/bit power efficiency, while communicating over a MDB memory channel at 36 Gb/s aggregate data rate