Late allocation and early release of physical registers

The register file is one of the critical components of current processors in terms of access time and power consumption. Among other things, the potential to exploit instruction-level parallelism is closely related to the size and number of ports of the register file. In conventional register renaming schemes, both register allocation and releasing are conservatively done, the former at the rename stage, before registers are loaded with values, and the latter at the commit stage of the instruction redefining the same register, once registers are not used any more. We introduce VP-LAER, a renaming scheme that allocates registers later and releases them earlier than conventional schemes. Specifically, physical registers are allocated at the end of the execution stage and released as soon as the processor realizes that there will be no further use of them. VP-LAER enhances register utilization, that is, the fraction of allocated registers having a value to be read in the future. Detailed cycle-level simulations show either a significant speedup for a given register file size or a reduction in the register file size for a given performance level, especially for floating-point codes, where the register file pressure is usually high.Peer ReviewedPostprint (published version

A Finite Exact Representation of Register Automata Configurations

A register automaton is a finite automaton with finitely many registers ranging from an infinite alphabet. Since the valuations of registers are infinite, there are infinitely many configurations. We describe a technique to classify infinite register automata configurations into finitely many exact representative configurations. Using the finitary representation, we give an algorithm solving the reachability problem for register automata. We moreover define a computation tree logic for register automata and solve its model checking problem.Comment: In Proceedings INFINITY 2013, arXiv:1402.661

Establishing a Regional AIS Application Specific Message Register

The goal of the Regional AIS Application Specific Message Register is to provide awareness of what applications exist, facilitate harmonization, and promote proper binary messaging for regional applications. To be hosted on the IALA website, establishing the Register will be a 3-step process: 1) Compile all existing AIS binaries into a Jcollection.K 2) Convert the JcollectionK into a Register. 3) Develop IALA guidance on best practices for creating and using AIS Binary Messages. Recommendations are provided in regard to: - Benefit of a web-based HTML user interface for input/output. - Use of XML to organize/format register applications in a consistent manner. - Having the collection/registration become a JloopK process. - Conforming to ISO standards to organize and manage the Register. - Benefit of a joint IMO-IALA register for both international and regional applications

Ancilla-Driven Universal Quantum Computation

We propose a method of manipulating a quantum register remotely with the help of a single ancilla that steers the evolution of the register. The fully controlled ancilla qubit is coupled to the computational register solely via a fixed unitary two-qubit interaction, E, and then measured in suitable bases. We characterize all interactions E that induce a unitary, step-wise deterministic measurement back-action on the register sufficient to implement any arbitrary quantum channel. Our scheme offers significant experimental advantages for implementing computations, preparing states and performing generalized measurements as no direct control of the register is required.Comment: 4 pages, 3 figure

THE REGISTER USED BY IMMIGRATION OFFICER OFIMMIGRATION \ud OFFICE IN MALANG

Language, as a tool of communication is needed to connect people in a community. That is why it is important to study language and things related with it. The development of language is influenced by the society itself, so they create many kinds of language variation, including dialect, jargon, slang, colloquial, vernacular, accent, pidgin, and register. The writer discussed one of those language variations that is register. Register is a stylistic variant of a language appropriate to a particular social setting. Register is often used by people in certain place. The writer studied about the registers used by immigration officer of immigration office in Malang. \ud This study used descriptive qualitative design to get the information. The subjects of the study were the three officers who involved in immigration office. In this research, the writer chose them because they have good knowledge on register used in that office. This used three kinds of instruments. There were non­participant observation, structured interview and document. They were used to seek the information and to get the necessary data related to register used by officer. \ud In analyzing data, the writer analyzed the data by interpreting, synthesizing, categorizing, and organizing data into patterns that produce a descriptive and narrative synthesis. \ud This study found out that total registers used by officers of immigration office are 22 registers. From the 22 registers, 9 registers grouped into formal registers and 13 registers can be grouped into informal registers. In this finding, another type of registers such as over­formal register, motherese, and reporting register were not found

Hierarchical clustered register file organization for VLIW processors

Technology projections indicate that wire delays will become one of the biggest constraints in future microprocessor designs. To avoid long wire delays and therefore long cycle times, processor cores must be partitioned into components so that most of the communication is done locally. In this paper, we propose a novel register file organization for VLIW cores that combines clustering with a hierarchical register file organization. Functional units are organized in clusters, each one with a local first level register file. The local register files are connected to a global second level register file, which provides access to memory. All intercluster communications are done through the second level register file. This paper also proposes MIRS-HC, a novel modulo scheduling technique that simultaneously performs instruction scheduling, cluster selection, inserts communication operations, performs register allocation and spill insertion for the proposed organization. The results show that although more cycles are required to execute applications, the execution time is reduced due to a shorter cycle time. In addition, the combination of clustering and hierarchy provides a larger design exploration space that trades-off performance and technology requirements.Peer ReviewedPostprint (published version

Simple circuit performs binary addition and subtraction

Ripple adder reduces the number of logic circuits required to preform binary addition and subtraction. The adder uses dual input and delayed output flip-flops in one register. The contents of this register are summed with those of a standard register through conventional AND/gates

Universal quantum computation by the unitary control of ancilla qubits and using a fixed ancilla-register interaction

We characterise a model of universal quantum computation where the register (computational) qubits are controlled by ancillary qubits, using only a single fixed interaction between register and ancillary qubits. No additional access is required to the computational register and the dynamics of both the register and ancilla are unitary. This scheme is inspired by the measurement-based ancilla-driven quantum computation of Anders et al. [PRA 82, 020301(R), 2010], but does not require measurements of the ancillas, and in this respect is similar to the original gate based model of quantum computation. We consider what possible forms this ancilla-register interaction can take, with a proof that the interaction is necessarily locally equivalent to SWAP combined with an entangling controlled gate. We further show which Hamiltonians can create such interactions and discuss two examples; the two-qubit XY Hamiltonian and a particular case of the XXZ Hamiltonian. We then give an example of a simple, finite and fault tolerant gate set for universal quantum computation in this model.Comment: 10 pages, Published versio

Binary to binary coded decimal converter

A binary coded input signal is converted to a binary coded decimal signal having N decades by employing N four bit shift registers. The bits of the input signal are sequentially supplied, in order, to the least significant position of the register for the units decade, with the most significant bit of the input signal being applied to the units register first. Each of the registers includes a right shift-parallel load mode control input terminal. In response to the sum of the values stored in each register and the binary value 0011 being less than the binary value 1000, the mode control input terminal is activated to shift the register contents one bit to the right. In response to the sum being greater than 1000, the mode control input terminal is activated to load the sum into the register