Non-Probabilistic Decision Making with Memory Constraints

In the model of choice, studied in this paper, the decision maker chooses the actions non-probabilistically in each period (Sarin and Vahid, 1999; Sarin, 2000). The action is chosen if it yields the biggest payoff according to the decision maker’s subjective assessment. Decision maker knows nothing about the process that generates the payoffs. If the decision maker remembers only recent payoffs, she converges to the maximin action. If she remembers all past payoffs, the maximal expected payoff action is chosen. These results hold for any possible dynamics of weights and are robust against the mistakes. The estimates of the rate of convergence reveal that in some important cases the convergence to the asymptotic behavior can take extremely long time. The model suggests simple experimental test of the way people memorize past experiences: if any weighted procedure is actually involved, it can possibly generate only two distinct modes of behavior.Adaptive learning; constrained memory; bandit problem; non-probabilistic choice

Analysing Compression Techniques for In-Memory Collaborative Filtering

Following the recent trend of in-memory data processing, it is a usual practice to maintain collaborative filtering data in the main memory when generating recommendations in academic and industrial recommender systems. In this paper, we study the impact of integer compression techniques for in-memory collaborative filtering data in terms of space and time efficiency. Our results provide relevant observations about when and how to compress collaborative filtering data. First, we observe that, depending on the memory constraints, compression techniques may speed up or slow down the performance of state-of-the art collaborative filtering algorithms. Second, after comparing different compression techniques, we find the Frame of Reference (FOR) technique to be the best option in terms of space and time efficiency under different memory constraints

High-level synthesis under I/O Timing and Memory constraints

The design of complex Systems-on-Chips implies to take into account communication and memory access constraints for the integration of dedicated hardware accelerator. In this paper, we present a methodology and a tool that allow the High-Level Synthesis of DSP algorithm, under both I/O timing and memory constraints. Based on formal models and a generic architecture, this tool helps the designer to find a reasonable trade-off between both the required I/O timing behavior and the internal memory access parallelism of the circuit. The interest of our approach is demonstrated on the case study of a FFT algorithm