An integrated circuit switch

Multi-chip integrated circuit switch consists of a GaAs photon-emitting diode in close proximity with S1 phototransistor. A high current gain is obtained when the transistor has a high forward common-emitter current gain

Metabolomics on integrated circuit

We have demonstrated a chip-based diagnostics tool for the quantification of metabolites, using specific enzymes, to study enzyme kinetics and calculate the Michaelis-Menten constant. An array of 256×256 ion-sensitive field effect transistors (ISFETs) fabricated in a complementary metal oxide semiconductor (CMOS) process is used for this prototype. We have used hexokinase enzyme reaction on the ISFET CMOS chip with glucose concentration in the physiological range of 0.05 mM – 231 mM and successfully studied the enzyme kinetics of hexokinase in detail. This will promote future research towards multiplexing enzyme-based metabolite quantification on a single chip, ultimately opening a pathway towards a personal metabolome machine

Automatic visual inspection system for microelectronics

A system for automatically inspecting an integrated circuit was developed. A device for shining a scanning narrow light beam at an integrated circuit to be inspected and another light beam at an accepted integrated circuit was included. A pair of photodetectors that receive light reflected from these integrated circuits, and a comparing system compares the outputs of the photodetectors

Integrated-circuit balanced parametric amplifier

Amplifier, fabricated on single dielectric substrate, has pair of Schottky barrier varactor diodes mounted on single semiconductor chip. Circuit includes microstrip transmission line and slot line section to conduct signals. Main features of amplifier are reduced noise output and low production cost

Integrated circuit reliability testing

A technique is described for use in determining the reliability of microscopic conductors deposited on an uneven surface of an integrated circuit device. A wafer containing integrated circuit chips is formed with a test area having regions of different heights. At the time the conductors are formed on the chip areas of the wafer, an elongated serpentine assay conductor is deposited on the test area so the assay conductor extends over multiple steps between regions of different heights. Also, a first test conductor is deposited in the test area upon a uniform region of first height, and a second test conductor is deposited in the test area upon a uniform region of second height. The occurrence of high resistances at the steps between regions of different height is indicated by deriving the measured length of the serpentine conductor using the resistance measured between the ends of the serpentine conductor, and comparing that to the design length of the serpentine conductor. The percentage by which the measured length exceeds the design length, at which the integrated circuit will be discarded, depends on the required reliability of the integrated circuit

Complementary DMOS-VMOS integrated circuit structure

A high speed CMOS formed on a single semiconductor substrate includes a DMOS having an asymmetric channel and a VMOS with a relatively short channel length. The short channel length of the VMOS is achieved by forming a double diffusion along one edge of a V groove, or ion implanting boron into the apex of the V groove and diffusing a single layer to a relatively deep depth along both edges of the groove

Substrate Optimization for Integrated Circuit Antennas

The reciprocity theorem and integral equation techniques are employed to determine the properties of integrated-circuit antennas. The effect of surface waves is considered for dipole and slot elements on substrates. The radiation and bandwidth of microstrip dipoles are optimized in terms of substrate thickness and permittivity

Integrated circuit random-access memory decoder

Decoder circuit with complementary-symmetry circuit configuration composed of MOS and n-p-n bipolar devices minimizes power consumption. Emitter-follower drive scheme results in low power dissipation and high speed operation

Integrated circuit interface for artificial skins

Artificial sensitive skins are intended to emulate the human skin to improve the skills of robots and machinery in complex unstructured environments. They are basically smart arrays of pressure sensors. As in the case of artificial retinas, one problem to solve is the management of the huge amount of information that such arrays provide, especially if this information should be used by a central processing unit to implement some control algorithms. An approach to manage such information is to increment the signal processing performed close to the sensor in order to extract the useful information and reduce the errors caused by long wires. This paper proposes the use of voltage to frequency converters to implement a quite straightforward analog to digital conversion as front end interface to digital circuitry in a smart tactile sensor. The circuitry commonly implemented to read out the information from a piezoresistive tactile sensor can be modified to turn it into an array of voltage to frequency converters. This is carried out in this paper, where the feasibility of the idea is shown through simulations and its performance is discussed.Gobierno de España TEC2006-12376-C02-01, TEC2006-1572

Integrated circuit flat-pack lead bender

Tool bends leads quickly and accurately for mounting on printed circuit boards. It has grooves and bend-angles aligned for particular circuit board applications