Standard cell layout with regular contact placement

The practicability and methodology of applying regularly placed contacts on layout design of standard cells are studied. The regular placement enables more effective use of resolution enhancement technologies, which in turn allows for a reduction of critical dimensions. Although placing contacts on a grid adds restrictions during cell layout, overall circuit area can be made smaller by a careful selection of the grid pitch, allowing slight contact offset, applying double exposure, and shrinking the minimum size and pitch. The contact level of 250 nm standard cells was shrunk by 10%, resulting in an area change ranging from -20% to +25% with an average decrease of 5% for the 84 cells studied. The areas of two circuits, a finite-impulse-response (FIR) filter and an add-compare-select (ACS) unit in the Viterbi decoder, decrease by 4% and 2%, respectively.published_or_final_versio

Optimization Of the Manufacturing Process for School Portfolios Through the Implementation of The Cellular Layout

One of the most common problems encountered in the manufacturing process is improper layout. About 30% of production time is wasted on transporting materials and products. The causes of this waste are problems in the disposition of stock and machines in production, that is, in the factory layout production of school desks became more efficient with the use of the cell layout. The result found was that with the implementation of the cell layout, there was an increase in the number of wallets produced and a reduction in the waste of materials. It is concluded that the. In this context, the production line based on the cellular layout has been an excellent ally, since the cells of this layout can improve the use of available space, without increasing costs due to major renovations or constructions. To prove such improvements, through the implementation of the cell layout, the PSL method (Systematic Layout Planning) was used, which follows steps such as data collection, analysis of necessary and available space, and factory limitations. With these stages of knowledge and analysis of the factory, it becomes possible to discard layouts that do not fit the characteristics of the company, whether related to financial resources, available space, and factory culture. Using the Chi-Square test for statistical analysis, it was possible to verify that the cell layout is an efficient optimization tool in the school desks production process, as it brought numerous benefits to the factory under studies, such as increased productivity, greater organization, and flexibility in the processes

Radial EBG Cell Layout for GPS Patch Antennas

A novel radial layout for mushroom-like electromagnetic-bandgap (EBG) cells surrounding a printed circularly-polarised patch antenna is proposed. Two radial EBG configurations surrounding a circular patch are compared to a reference patch on a conventional ground plane of the same dimension. The radial shape and displacement of the EBG cells around the patch offers improvements in terms of gain and axial-ratio compared to the reference antenna and is more suitable for circular geometries compared to conventional Cartesian layouts. In particular, the distance between the patch and the surrounding EBG cells is independent of the cell period, which can be arbitrarily chosen, and the overall layout offers footprint reduction

Facility Layout Problem for Cellular Manufacturing Systems

Good layout plan leads to in improve machine utilization, part demand quality, efficient setup time, less work-in-process inventory and material handling cost. Cellular Manufacturing (CM) is an application of GTCM is the combination of job shop and/or flow shop. Facility Layout Problem (FLP) for CMS includes both inter-cell layout and intra-cell layout. A bi-level mixed-integer non-linear programming continuous model has been formulated to fully define the problem and the relationship between intra-cell and inter-cell layout design. Facilities are assumed unequal size; operation sequences, part demands, overlap elimination, aisle are considered. The problem is NP-hard; hence, a simulated annealing meta-heuristic employing a novel constructive radial-based heuristic for initialization have been designed and implemented. For the first time, a novel heuristic algorithm has been designed to allocate and displace facilities in radial direction. In order to improve the search efficiency of the developed SA algorithm, the cell size used in the initialization heuristic algorithm is assumed twice as that of the original size of the cells. A real case study from the metal cutting inserts industry has been used. Results demonstrate the superiority of the developed SA algorithm against rival comparable meta-heuristics and algorithms from the literature

Quantitative Analysis of AGV System in FMS Cell Layout

Material handling is a specialised activity for a modern manufacturing concern. Automated guided vehicles (AGVs) are invariably used for material handling in flexible manufacturing Systems (FMSs) due to their flexibility. The quantitative analysis of an AGV system is useful for determining the material flow rates, operation times, length of delivery, length of empty move of AGV and the number of AGVs required for a typical FMS cell layout. The efficiency of the material handling system, such as AGV can be improved by reducing the length of empty move. The length of empty move of AGV depends upon despatching and scheduling methods. If these methods of AGVs are not properly planned, the length of empty move of AGV is greater than the length of delivery .This results in increase in material handling time which in turn increases the number of AGVs required in FMS cell. This paper presents a method for optimising the length of empty travel of AGV in a typical FMS cell layout

Testability enhancement of a basic set of CMOS cells

Testing should be evaluated as the ability of the test patterns to cover realistic faults, and high quality IC products demand high quality testing. We use a test strategy based on physical design for testability (to discover both open and short faults, which are difficult or even impossible to detect). Consequentially, layout level design for testability (LLDFT) rules have been developed, which prevent the faults, or at least reduce the chance of their appearing. The main purpose of this work is to apply a practical set of LLDFT rules to the library cells designed by the Centre Nacional de Microelectrònica (CNM) and obtain a highly testable cell library. The main results of the application of the LLDFT rules (area overheads and performance degradation) are summarized and the results are significant since IC design is highly repetitive; a small effort to improve cell layout can bring about great improvement in design

A genetic algorithm approach to designing and modelling of a multi-functional fractal manufacturing layout

A dynamic and optimal shop floor design, modelling and implementation is key to achieving successful Fractal Manufacturing System (FrMS). To build adaptive and fault-tolerant fractal layout, attention is paid to issues of shop floor planning, function layout, determination of capacity level, cell composition planning and flow distances of products. A full fledged FrMS. layout is multi-functional and is capable of producing a variety of products with minimal reconfiguration. This paper is part and a progression of an on-going project whereby Genetic Algorithm (GA) is adopted to design and model a flexible and multi-functional FrMS floor layout. GA is used in the project for modeling and simulation. The design implementation is done using MATLAB. The result is a fault tolerant configuration that self-regulates and adapts to unpredictable changes in the manufacturing environment arising from lead time reduction pressure, inventories, product customization and other challenges of a dynamic and volatile operational environment

Cell replication and redundancy elimination during placement for cycle time optimization

This paper presents a new timing driven approach for cell replication tailored to the practical needs of standard cell layout design. Cell replication methods have been studied extensively in the context of generic partitioning problems. However, until now it has remained unclear what practical benefit can be obtained from this concept in a realistic environment for timing driven layout synthesis. Therefore, this paper presents a timing driven cell replication procedure, demonstrates its incorporation into a standard cell placement and routing tool and examines its benefit on the final circuit performance in comparison with conventional gate or transistor sizing techniques. Furthermore, we demonstrate that cell replication can deteriorate the stuck-at fault testability of circuits and show that stuck-at redundancy elimination must be integrated into the placement procedure. Experimental results demonstrate the usefulness of the proposed methodology and suggest that cell replication should be an integral part of the physical design flow complementing traditional gate sizing techniques

Methodology for standard cell compliance and detailed placement for triple patterning lithography

As the feature size of semiconductor process further scales to sub-16nm technology node, triple patterning lithography (TPL) has been regarded one of the most promising lithography candidates. M1 and contact layers, which are usually deployed within standard cells, are most critical and complex parts for modern digital designs. Traditional design flow that ignores TPL in early stages may limit the potential to resolve all the TPL conflicts. In this paper, we propose a coherent framework, including standard cell compliance and detailed placement to enable TPL friendly design. Considering TPL constraints during early design stages, such as standard cell compliance, improves the layout decomposability. With the pre-coloring solutions of standard cells, we present a TPL aware detailed placement, where the layout decomposition and placement can be resolved simultaneously. Our experimental results show that, with negligible impact on critical path delay, our framework can resolve the conflicts much more easily, compared with the traditional physical design flow and followed layout decomposition