Capacitance multiplier and filter synthesizing network

A circuit using a differential amplifier multiplies the capacitance of a discrete interating capacitor by (r sub 1 + R sub 2)/R sub 2, where R sub 1 and R sub 2 are values of discrete resistor coupling an input signal e sub 1 of the amplifier inputs. The output e sub 0 of the amplifier is fed back and added to the signal coupled by the resistor R sub 2 to the amplifier through a resistor of value R sub 1. A discrete resistor R sub x may be connected in series for a lag filter, and a discrete resistor may be connected in series with the capacitor for a lead-lag filter. Voltage dividing resistors R sub a and R sub b may be included in the feedback circuit of the amplifier output e sub o to independently adjust the circuit gain e sub i/e sub o

Improved capacitance multiplier circuit

Circuit multiplies capacitance without increasing overall circuit gain. In addition, circuit may be designed to include lag or lead/lag transfer function and independent gain adjustment

Novel Floating General Element Simulators Using CBTA

In this study, a novel floating frequency dependent negative resistor (FDNR), floating inductor, floating capacitor and floating resistor simulator circuit employing two CBTAs and three passive components is proposed. The presented circuit can realize floating FDNR, inductor, capacitor or resistor depending on the passive component selection. Since the passive elements are all grounded, this circuit is suitable for fully integrated circuit design. The circuit does not require any component matching conditions, and it has a good sensitivity performance with respect to tracking errors. Moreover, the proposed FDNR, inductance, capacitor and resistor simulator can be tuned electronically by changing the biasing current of the CBTA or can be controlled through the grounded resistor or capacitor. The high-order frequency dependent element simulator circuit is also presented. Depending on the passive component selection, it realizes high-order floating circuit defining as V(s) = snAI(s) or V(s) = s-nBI(s). The proposed floating FDNR simulator circuit and floating high-order frequency dependent element simulator circuit are demonstrated by using PSPICE simulation for 0.25 μm, level 7, TSMC CMOS technology parameters

Tunable Fractional-Order Capacitance Multiplier Using Current Gain Adjustment

This paper brings new solution of linearly adjustable fractional-order capacitance multiplier. The adjustable current gain, linear in wide range of input current and with linear dependence on driving voltage, serves for these purposes and offers one-decade variation of equivalent capacity (pseudo-capacitance) between 24 and 429 F/sec^0.75 . The operational range was tested by PSpice simulations and by measurement using RC approximant of constant phase element of the order 0.25 in bandwidth from 20 Hz up to 1 MHz

Analog interface based on capacitance multiplier for capacitive sensors and application to evaluate the quality of oils

Currently, interdigital capacitive (IDC) sensors are widely used in science, industry and technology. To measure the changes in capacitance in these sensors, many methods such as differentiation, phase delay between two signals, capacitor charging/discharging, oscillators and switching circuits have been proposed. These techniques often use high frequencies and high complexity to measure small capacitance changes of fF or aF with high sensitivity. An analog interface based on a capacitance multiplier for capacitive sensors is presented. This study includes analysis of the interface error factors, such as the error due to the components of the capacitance multiplier, parasitic capacitances, transient effects and non-ideal parameters of OpAmp. A design approach based on an IDC sensor to measure the quality of edible oils is presented and implemented. The quality relates to the total polar compounds (TPC) and consequently to relative electrical permittivity ${\varepsilon }_{r}$ of the oils. A measurement system has been implemented to measure the capacitance of the IDC sensor, which depended on ${\varepsilon }_{r}$. The simulation and experimental results showed that, for a capacitance multiplication factor equal to 1000, changes of 3.3 µs/100 fF can be achieved with an acceptable level of noise, which can be easily measured by a microcontroller

Simple Three-Input Single-Output Current-Mode Universal Filter Using Single VDCC

This paper presents a second-order current-mode filter with three-inputs and single-output current using single voltage differencing current conveyors (VDCC) along with one resistor and two grounded capacitors. The design of presented filter emphasizes on the use of a single active element without the multiple terminals VDCC which is convenient to implement the VDCC using commercially available IC for the practical test. Also, it can reduce the current tracking error at current output port and can reduce the number of transistor in the VDCC. The proposed filter can realize all the five generic filter responses, namely, band-pass (BP), band-reject (BR), low-pass (LP), high-pass (HP), and all-pass (AP) functions from the same configuration under various conditions in terms of three input current signals. Furthermore, the natural frequency and quality factor are electronically controlled. The output current node exhibits high impedance. Besides, the non-ideal case is also investigated. The simulation and experimental results using VDCC constructed from commercially available IC can validate the theoretical analyses