Low-Jitter Clock Multiplication: a Comparioson between PLLs and DLLs

This paper shows that, for a given power budget, a practical phase-locked loop (PLL)-based clock multiplier generates less jitter than a delay-locked loop (DLL) equivalent. This is due to the fact that the delay cells in a PLL ring-oscillator can consume more power per cell than their counterparts in the DLL. We can show that this effect is stronger than the notorious jitter accumulation effect that occurs in the voltage-controlled oscillator (VCO) of a PLL. First, an analysis of the stochastic-output jitter of the architectures, due to the most important noise sources, is presented. Then, another important source of jitter in a DLL-based clock multiplier is treated, namely the stochastic mismatch in the delay cells which compose the DLL voltage-controlled delay line (VCDL). An analysis is presented that relates the stochastic spread of the delay of the cells to the output jitter of the clock multiplier. A circuit design technique, called impedance level scaling, is then presented which allows the designer to optimize the noise and mismatch behavior of a circuit, independently from other specifications such as speed and linearity. Applying this technique on a delay cell design yields a direct tradeoff between noise induced jitter and power usage, and between stochastic mismatch induced jitter and power usage

Deterministic and stochastic features of rhythmic human movement

The dynamics of rhythmic movement has both deterministic and stochastic features. We advocate a recently established analysis method that allows for an unbiased identification of both types of system components. The deterministic components are revealed in terms of drift coefficients and vector fields, while the stochastic components are assessed in terms of diffusion coefficients and ellipse fields. The general principles of the procedure and its application are explained and illustrated using simulated data from known dynamical systems. Subsequently, we exemplify the method's merits in extracting deterministic and stochastic aspects of various instances of rhythmic movement, including tapping, wrist cycling and forearm oscillations. In particular, it is shown how the extracted numerical forms can be analysed to gain insight into the dependence of dynamical properties on experimental conditions

Extrapulmonary Tuberculosis by Nationality, the Netherlands, 1993–2001

The growth of the number of inhabitants with a non-Western ethnic background most likely explains the growth of extrapulmonary TB in the Netherlands

A 2.5-10-GHz clock multiplier unit with 0.22-ps RMS jitter in standard 0.18-μm CMOS

This paper demonstrates a low-jitter clock multiplier unit that generates a 10-GHz output clock from a 2.5-GHz reference clock. An integrated 10-GHz LC oscillator is locked to the input clock, using a simple and fast phase detector circuit that overcomes the speed limitation of a conventional tri-state phase frequency detector due to the lack of an internal feedback loop. A frequency detector guarantees PLL locking without degenerating jitter performance. The clock multiplier is implemented in a standard 0.18-μm CMOS process and achieves a jitter generation of 0.22 ps while consuming 100 mW power from a 1.8-V supply