АДРЕСНЫЕ ПОСЛЕДОВАТЕЛЬНОСТИ ДЛЯ МНОГОКРАТНОГО ТЕСТИРОВАНИЯ ОЗУ

A universal approach for generation of address sequences with specified properties is proposed and analyzed. A modified version of the Antonov and Saleev algorithm for Sobol sequences genera-tion is chosen as a mathematical description of the proposed method. Within the framework of the proposed universal approach, the Sobol sequences form a subset of the address sequences. Other sub-sets are also formed, which are Gray sequences, anti-Gray sequences, counter sequences and sequenc-es with specified properties.Предлагается универсальный метод генерирования адресных последовательностей с задан-ными свойствами для многократных маршевых тестов оперативных запоминающих устройств. В качестве математической модели используется модификация экономичного способа Антонова и Салеева для формирования последовательностей Соболя. В рамках предлагаемой модели последова-тельности Соболя являются подмножеством адресных последовательностей, наряду с которыми формируются последовательности кода Грея, анти-Грея, пересчетные и ряд других последователь-ностей, в том числе последовательности с заданными свойствами

КВАЗИСЛУЧАЙНОЕ ТЕСТИРОВАНИЕ ВЫЧИСЛИТЕЛЬНЫХ СИСТЕМ

Various modified random testing approaches have been proposed for computer system testing in the black box environment. Their effectiveness has been evaluated on the typical failure patterns by employing three measures, namely, P-measure, E-measure and F-measure. A quasi-random testing, being a modified version of the random testing, has been proposed and analyzed. The quasi-random Sobol sequences and modified Sobol sequences are used as the test patterns. Some new methods for Sobol sequence generation have been proposed and analyzed.Анализируются причинно-следственные связи при возникновении неисправностей вычисли-тельных систем. Даются определения понятий «неисправность», «ошибка» и «неисправное поведение вычислительных систем», показывается их общность для программной и аппаратной частей вычислительных систем. Рассматривается классификация обобщенных входных тестовых воздей-ствий на три категории: точечные тестовые наборы, узкополосные тестовые наборы и блочные тестовые наборы. Приводится анализ методов тестирования вычислительных систем по методике черного ящика, показывается эффективность использования квазислучайного тестирования. Анали-зируются и предлагаются методы формирования квазислучайных тестовых воздействий

Two-run RAM march testing with address decimation

Conventional march memory tests have high fault coverage, especially for simple faults like stack-at fault (SAF), transition fault (TF) or coupling fault (CF). The same-time standard march tests, which are based on only one run, are becoming insufficient for complex faults like pattern-sensitive faults (PSFs). To increase fault coverage, the multi-run transparent march test algorithms have been used. This solution is especially suitable for built-in self-test (BIST) implementation. The transparent BIST approach presents the incomparable advantage of preserving the content of the random access memory (RAM) after testing. We do not need to save the memory content before the test session or to restore it at the end of the session. Therefore, these techniques are widely used in critical applications (medical electronics, railway control, avionics, telecommunications, etc.) for periodic testing in the field. Unfortunately, in many cases, there is very limited time for such test sessions. Taking into account the above limitations, we focus on short, two-run march test procedures based on counter address sequences. The advantage of this paper is that it defines requirements that must be taken into account in the address sequence selection process and presents a deeply analytical investigation of the optimal address decimation parameter. From the experiments we can conclude that the fault coverage of the test sessions generated according to the described method is higher than in the case of pseudorandom address sequences. Moreover, the benefit of this solution seems to be low hardware overhead in implementation of an address generator

Methods of synthesis of controlled random tests

Controlled random tests, methods of their generation, main criteria used for their synthesis, such as the Hamming distance and the Euclidean distance, as well as their application to the testing of both hardware and software systems are discussed. Available evidences suggest that high computational complexity is one of the main drawbacks of these methods. Therefore we propose a technique to overcome this problem. A method for synthesizing multiple controlled random tests based on the use of the initial random test and addition operation has been proposed. The resulting multiple tests can be interpreted as a single controlled random test. The complexity of its construction is significantly lower than the complexity of the construction of classical random tests. Examples of generated tests as well as estimates of their effectiveness compared to other solutions have been presented in experimental studies

Generowanie wieloprzebiegowych kontrolowanych testów losowych

Controlled Random Tests and methods for their generation have been analyzed and investigated. The similarities of all known controlled random testing approaches are shown. The new method and algorithm for Multiple Controlled Random Tests have been proposed and analyzed

Synthesis of a Test Generator for a Built-ln Self-Test Scheme

This paper presents a new algorithm for the automated synthesis of pseudo-random test patterns generators for Built-ln Self Test schemes with a mixed testmode. The experimental resulls showan opportunity of using the given method on a design stage of circuits producing In this paper it is shown that an appropriat selection of test pattern generator can significantly reduce the hardware requirements of deterministic part

Optimal controlled random tests

Controlled random tests, methods of their generation, main criteria used for their synthesis, such as the Hamming distance and the Euclidean distance, as well as their application to the testing of both hardware and software systems are discussed. Available evidences suggest that high computational complexity is one of the main drawbacks of these methods. Therefore we propose a technique to overcome this problem. In the paper we propose the algorithm for optimal controlled random tests generation. Both experimental and analytical investigation clearly show the high efficiency of proposed solution especially for the multi-run tests with small number of iterations. The given tests can be applied for hardware and software testing but it seems they may be particularly interesting from the perspective of the effective detection of pattern sensitive faults in RAMs

Synthesis of Test Sequences with a Given Switching Activity

The relevance of using test sequences with a given switching activity is discussed. As a mathematical model for generating the tests, a modification of the Antonov–Saleev method for generating Sobol sequences is used. It is based on the use of maximum-rank generating matrices the form of which determines the main properties of the sequences. It is shown that the construction of a generating matrix is reduced to the problem of partitioning an integer, and an algorithm for splitting into summands of a given form is proposed. Procedures for modifying the partition of an integer into summands and for modifying the value of switching activity are introduced. Three problems are stated for the synthesis of generators of test sequences with a given switching activity. Examples of using the proposed methods and experimental results are considered

Псевдоисчерпывающее тестирование запоминающих устройств на базе маршевых тестов типа March A

The relevance of testing of memory devices of modern computing systems is shown. The methods and algorithms for implementing test procedures based on classical March tests are analyzed. Multiple March tests are highlighted to detect complex pattern-sensitive memory faults. To detect them, the necessary condition that test procedures must satisfy to deal complex faults, is substantiated. This condition is in the formation of a pseudo-exhaustive test for a given number of arbitrary memory cells. We study the effectiveness of single and double application of tests like MATS ++, March C– and March A, and also give its analytical estimates for a different number of k ≤ 10 memory cells participating in a malfunction. The applicability of the mathematical model of the combinatorial problem of the coupon collector for describing multiple memory testing is substantiated. The values of the average, minimum, and maximum multiplicity of multiple tests are presented to provide an exhaustive set of binary combinations for a given number of arbitrary memory cells. The validity of analytical estimates is experimentally shown and the high efficiency of the formation of a pseudo-exhaustive coverage by tests of the March A type is confirmed.Показывается актуальность тестирования запоминающих устройств современных вычислительных систем. Анализируются методы и алгоритмы реализации тестовых процедур на базе классических маршевых тестов. Выделяются многократные маршевые тесты, позволяющие обнаруживать сложные кодочувствительные неисправности памяти. Для их обнаружения обосновывается необходимое условие, которому должны удовлетворять тестовые процедуры для покрытия сложных неисправностей. Это условие заключается в формировании псевдоисчерпывающего теста для заданного количества произвольных ячеек памяти. Исследуется эффективность однократного и двукратного применения тестов типа MATS++, March C- и March A, а также приводятся ее аналитические оценки для различного количества k ≤10 ячеек памяти, участвующих в неисправности. Обосновывается применимость математической модели комбинаторной задачи собирателя купонов для описания многократного тестирования памяти. Приводятся значения средней, минимальной и максимальной кратности многократных тестов для обеспечения исчерпывающего множества двоичных комбинаций для заданного числа произвольных ячеек памяти. Экспериментально показывается справедливость аналитических оценок и подтверждается высокая эффективность формирования псевдоисчерпывающего покрытия тестами типа March A

Universal Address Sequence Generator for Memory Built-in Self-test

This paper presents the universal ad-dress sequence generator (UASG) for memorybuilt-in-self-test. The studies are based on the proposed universal method for generating address se-quences with the desired properties for multirun march memory tests. As a mathematical model, a modification of the recursive relation for quasi-random sequence generation is used. For this model, a structural diagram of the hardware implementation is given, of which the basis is a storage device for storing so-called direction numbers of the generation matrix. The form of the generation matrix determines the basic properties of the generated ad-dress sequences. The proposed UASG generates a wide spectrum of different address sequences, including the stand-ard ones, such as linear, address com-plement, gray code, worst-case gate delay, 2i, next address, and pseudoran-dom. Examples of the use of the pro-posed methods are considered. The result of the practical implementation of the UASG is presented, and the main characteristics are evaluated