High density circuit technology

Acquisition of polyimide materials for inter-metal dielectrics was obtained from three vendors, with considerable evaluation conducted on the Dupont PI2550 material. Experimental results indicate this material can be patterned using contact printing to line width far below 0.1 mils. Optimum line width is acquired using plasma etch equipment. Metal lift-off experiments on thermal evaporated films were optimized for application to sputtered deposited films. Alternate metal-lift-off experiments are proposed for future investigation. Dry processing equipment studies and future trends in VLSI fabrication techniques are on-going

High density circuit technology

Polyimide dielectric materials were acquired for comparative and evaluative studies in double layer metal processes. Preliminary experiments were performed. Also, the literature indicates that sputtered aluminum films may be successfully patterned using the left-off technique provided the substrate temperature remains low and the argon pressure in the chamber is relatively high at the time of sputtering. Vendors associated with dry processing equipment are identified. A literature search relative to future trends in VLSI fabrication techniques is described

Post heat treatment effects on double layer metal structures for VLSI applications

The realization of high yield double layer metal systems using wet chemistry processes and the ability to extend yields beyond that attainable with wet chemistry by means of post sintering processes at temperatures below 500 C for potential applications in very large scale integration structures were studied. Yields in excess of 98% and average total contact resistance of less than 150 ohms and 200 ohms were realized for a series of 560 vias of 0.5 X 0.5 mils and 0.2 X 0.2 mils in size, respectively

A study of trends and techniques for space base electronics

The use of dry processing and alternate dielectrics for processing wafers is reported. A two dimensional modeling program was written for the simulation of short channel MOSFETs with nonuniform substrate doping. A key simplifying assumption used is that the majority carriers can be represented by a sheet charge at the silicon dioxide-silicon interface. In solving current continuity equation, the program does not converge. However, solving the two dimensional Poisson equation for the potential distribution was achieved. The status of other 2D MOSFET simulation programs are summarized

Trends and Techniques for Space Base Electronics

Simulations of various phosphorus and boron diffusions in SOS were completed and a sputtering system, furnaces, and photolithography related equipment were set up. Double layer metal experiments initially utilized wet chemistry techniques. By incorporating ultrasonic etching of the vias, premetal cleaning a modified buffered HF, phosphorus doped vapox, and extended sintering, yields of 98% were obtained using the standard test pattern. A two dimensional modeling program was written for simulating short channel MOSFETs with nonuniform substrate doping. A key simplifying assumption used is that the majority carriers can be represented by a sheet charge at the silicon dioxide silicon interface. Although the program is incomplete, the two dimensional Poisson equation for the potential distribution was achieved. The status of other Z-D MOSFET simulation programs is summarized

High density circuit technology, part 3

Dry processing - both etching and deposition - and present/future trends in semiconductor technology are discussed. In addition to a description of the basic apparatus, terminology, advantages, glow discharge phenomena, gas-surface chemistries, and key operational parameters for both dry etching and plasma deposition processes, a comprehensive survey of dry processing equipment (via vendor listing) is also included. The following topics are also discussed: fine-line photolithography, low-temperature processing, packaging for dense VLSI die, the role of integrated optics, and VLSI and technology innovations

High density circuit technology, part 1

The metal (or dielectric) lift-off processes used in the semiconductor industry to fabricate high density very large scale integration (VLSI) systems were reviewed. The lift-off process consists of depositing the light-sensitive material onto the wafer and patterning first in such a manner as to form a stencil for the interconnection material. Then the interconnection layer is deposited and unwanted areas are lifted off by removing the underlying stencil. Several of these lift-off techniques were examined experimentally. The use of an auxiliary layer of polyimide to form a lift-off stencil offers considerable promise

High density circuit technology, part 4

An accurate study and evaluation of dielectric thin films is conducted in order to find the material or combination of materials which would optimize NASA'S double layer metal process. Emphasis is placed on polyimide dielectrics because of their reported outstanding dielectric characteristics (including electrical, chemical, thermal, and mechanical) and ease of processing, as well as their rapid acceptance by the semiconductor industry