2,964 research outputs found

    Inertial and Degradation Delay Model for CMOS Logic Gates

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    The authors present the Inertial and Degradation Delay Model (IDDM) for CMOS digital simulation. The model combines the Degradation Delay Model presented in previous papers with a new algorithm to handle the inertial effect, and is able to take account of the propagation and filtering of arbitrarily narrow pulses (glitches, etc.). The model clearly overcomes the limitations of conventional approaches

    Discursos leídos ante la Real Academia de Ciencias Morales y Políticas en la recepción pública del señor conde de Casa-Valencia, el viernes 29 de junio de 1877.

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    Copia digital. Valladolid : Junta de Castilla y León. Consejería de Cultura y Turismo, 2014Contiene: Discurso del Excmo. Señor Don Manuel Alonso Martíne

    Comedia. Bernardo del Carpio en Francia / de Don Lope de Llano

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    Segun Barrera el autor es Lope de LiañoDatos de i mp. obtenidos del colofónTexto a 2 colSign.: A-C4En la port. sello de imprenta: "Se hallara en la Imprenta de Orga, calle de las Barcas, en Valencia, nº 13

    HALOTIS: high accuracy LOgic TIming simulator with inertial and degradation delay model

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    This communication presents HALOTIS, a novel high accuracy logic timing simulation tool, that incorporates a new simulation algorithm based on different concepts for transitions and events. This new simulation algorithm is intended for including the inertial and degradation delay models. Simulation results are very similar to those obtained by electrical simulators, and show a higher accuracy compared to conventional delay models implemented in current logic simulators.Ministerio de Ciencia y Tecnología TIC 2000-135
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