Stability of a trapped atom clock on a chip

We present a compact atomic clock interrogating ultracold 87Rb magnetically trapped on an atom chip. Very long coherence times sustained by spin self-rephasing allow us to interrogate the atomic transition with 85% contrast at 5 s Ramsey time. The clock exhibits a fractional frequency stability of $5.8\times 10^{-13}$ at 1 s and is likely to integrate into the $1\times10^{-15}$ range in less than a day. A detailed analysis of 7 noise sources explains the measured frequency stability. Fluctuations in the atom temperature (0.4 nK shot-to-shot) and in the offset magnetic field ($5\times10^{-6}$ relative fluctuations shot-to-shot) are the main noise sources together with the local oscillator, which is degraded by the 30% duty cycle. The analysis suggests technical improvements to be implemented in a future second generation set-up. The results demonstrate the remarkable degree of technical control that can be reached in an atom chip experiment.Comment: 12 pages, 11 figure

Control Requirements and Benchmarks for Quantum Error Correction

Reaching useful fault-tolerant quantum computation relies on successfully implementing quantum error correction (QEC). In QEC, quantum gates and measurements are performed to stabilize the computational qubits, and classical processing is used to convert the measurements into estimated logical Pauli frame updates or logical measurement results. While QEC research has concentrated on developing and evaluating QEC codes and decoding algorithms, specification and clarification of the requirements for the classical control system running QEC codes are lacking. Here, we elucidate the roles of the QEC control system, the necessity to implement low latency feed-forward quantum operations, and suggest near-term benchmarks that confront the classical bottlenecks for QEC quantum computation. These benchmarks are based on the latency between a measurement and the operation that depends on it and incorporate the different control aspects such as quantum-classical parallelization capabilities and decoding throughput. Using a dynamical system analysis, we show how the QEC control system latency performance determines the operation regime of a QEC circuit: latency divergence, where quantum calculations are unfeasible, classical-controller limited runtime, or quantum-operation limited runtime where the classical operations do not delay the quantum circuit. This analysis and the proposed benchmarks aim to allow the evaluation and development of QEC control systems toward their realization as a main component in fault-tolerant quantum computation.Comment: 21+9(SM) pages, 6+3(SM) figure

Quantum-classical processing and benchmarking at the pulse-level

Towards the practical use of quantum computers in the NISQ era, as well as the realization of fault-tolerant quantum computers that utilize quantum error correction codes, pressing needs have emerged for the control hardware and software platforms. In particular, a clear demand has arisen for platforms that allow classical processing to be integrated with quantum processing. While recent works discuss the requirements for such quantum-classical processing integration that is formulated at the gate-level, pulse-level discussions are lacking and are critically important. Moreover, defining concrete performance benchmarks for the control system at the pulse-level is key to the necessary quantum-classical integration. In this work, we categorize the requirements for quantum-classical processing at the pulse-level, demonstrate these requirements with a variety of use cases, including recently published works, and propose well-defined performance benchmarks for quantum control systems. We utilize a comprehensive pulse-level language that allows embedding universal classical processing in the quantum program and hence allows for a general formulation of benchmarks. We expect the metrics defined in this work to form a solid basis to continue to push the boundaries of quantum computing via control systems, bridging the gap between low-level and application-level implementations with relevant metrics.Comment: 22 page

Atom chips pour la métrologie

This thesis covers two main subjects: the evaluation of the stability of a Trapped Atom Clock on a Chip (TACC) and the expansion of this technology towards creating an atom interferometer on the same chip. The combination of a clock and an interferometer on the same chip constitutes the basis for the realization of atom-based integrated inertial navigation units. Previous work installed the clock operation and discovered, among others, very long coherence times, which allow Ramsey interrogations of up to 5 s, a prerequisite for high stability operation. I present the first thorough evaluation of the clock stability. Together with my predecessor we have demonstrated relative frequency fluctuations of 5.8 10-13 at 1 s integrating down to 6 10-15 at 30,000 s. The second part of this thesis aims to expand the versatility of our atom chip to create an atom interferometer. I have studied various interferometer schemes using microwave dressed potentials and implemented these to the set-up. The first scheme, following work by P. Treutlein et al., involves displacing one of the clock states vertically during a Ramsey clock sequence thereby allowing the measurement of potential gradients by exploiting the differential frequency shift accumulated between the two states. Ramsey fringes where recorded for different durations of the splitting, resulting in a clear signal of the wavepacket separation. The second scheme uses microwave dressing to generate a double well potential in one of the clock states and a single well in the other. Starting in the single well, a π-pulse on the clock transition constitutes the beam splitter and leads to a spatial separation for the same internal state.Cette thèse porte sur deux sujets principaux: l'évaluation de la stabilité d'une horloge sur microcircuit utilisant des atomes piégés (Trapped Atom Clock on a Chip - TACC) et l'extension de cette technologie vers la réalisation d'un interféromètre atomique sur la même puce. Cette combinaison constitue la base pour la réalisation de capteurs inertiels intégrés pour la navigation. Des travaux antérieurs ont installé l'horloge et ont découvert, entre autres, des temps de cohérence très longs, qui permettent une interrogation Ramsey jusqu'à 5 s, une condition préalable pour le fonctionnement à grande stabilité. Je présente ici la première évaluation approfondie de la stabilité de l'horloge. Avec mon prédécesseur, nous avons démontré les fluctuations de fréquences relatives de 5.8 10-13 à 1 s intégrant jusqu'à 6 10-15 à 30000 s.La deuxième partie de cette thèse vise à étendre la polyvalence de notre puce atomique pour créer un interféromètre. J'ai étudié divers régimes d'interféromètres en utilisant des potentiels habillés par microondes. Le premier régime consiste à déplacer l'un des états d'horloge verticalement pendant une séquence d'horloge Ramsey. Ceci permet la mesure de gradients de potentiel en exploitant la différence de fréquences entre les deux états. Le second régime utilise des champs microondes pour générer un potentiel de double puits dans l'un des états d'horloge et un seul puits dans l'autre.À partir du seul puits, un pulse-π sur la transition d'horloge constitue la séparatrice de l'interféromètre et conduit une séparation spatiale tout en préservant le même état interne pour les deux bras de l'interféromètre

Cold-atom-based commercial microwave clock at the 10-15 level

International audienc

Cold-atom-based commercial microwave clock at the 10-15 level

International audienc