DFT Techniques and Automation for Asynchronous NULL Conventional Logic Circuits

Conventional automatic test pattern generation (ATPG) algorithms fail when applied to asynchronous NULL convention logic (NCL) circuits due to the absence of a global clock and presence of more state-holding elements, leading to poor fault coverage. This paper presents a design-for-test (DFT) approach aimed at making asynchronous NCL designs testable using conventional ATPG programs. We propose an automatic DFT insertion flow (ADIF) methodology that performs scan and test point insertion on NCL designs to improve test coverage, using a custom ATPG library. Experimental results show significant increase in fault coverage for NCL cyclic and acyclic pipelined designs

Automated energy calculation and estimation for delayinsensitive digital circuits

Abstract With increasingly smaller feature sizes and higher on-chip densities, the power dissipation of VLSI systems has become a primary concern for designers. This paper first describes a procedure to simulate a transistor-level design using a VHDL testbench, and then presents a fast and efficient energy estimation approach for delay-insensitive (DI) systems, based on gate-level switching. Specifically, the VHDL testbench reads the transistor-level design's outputs and supplies the inputs accordingly, also allowing for automatic checking of functional correctness. This type of transistor-level simulation is absolutely necessary for asynchronous circuits because the inputs change relative to handshaking signals, which are not periodic, instead of changing relative to a periodic clock pulse, as do synchronous systems. The method further supports automated calculation of power and energy metrics. The energy estimation approach produces results three orders of magnitude faster than transistor-level simulation, and has been automated and works with standard industrial design tool suites, such as Mentor Graphics and Synopsys. Both methods are applied to the NULL Convention Logic (NCL) DI paradigm, and are first demonstrated using a simple NCL sequencer, and then tested on a number of different NCL 4-bit  4-bit unsigned multiplier architectures. Energy per operation is automatically calculated for both methods, using an exhaustive testbench to simulate all input combinations and to check for functional correctness. The results show that both methods produce the desired output for all circuits, and that the gate-level switching approach developed herein produces results more than 1000 times as fast as transistor-level simulation, that fall within the range obtained by two different industry-standard transistor-level simulators. Hence, the developed energy estimation method is extremely useful for quickly determining how architecture changes affect energy usage.

Hands-On Projects and Exercises to Strengthen Understanding of Basic Computer Engineering Concepts

The Introduction to Computer Engineering course at the University of Missouri-Rolla provides a thorough understanding of basic digital logic analysis and design. The course covers: digital numbering systems, Boolean algebra, function minimization using Karnaugh maps (K-maps), memory elements, and sequential logic design. Students\u27 grades are determined by their performance on homework assignments, quizzes, and in-class examinations. A laboratory course (optional for all but EE and CpE majors) supplements the lecture by providing experiments that include analysis and design using Mentor Graphics and FPGAs. While the laboratory is a very useful supplement to the lecture, almost half the students taking the lecture are not required to take the laboratory and there is not sufficient time in the laboratory schedule to introduce significant design elements. In Fall 2004, hands-on group projects, for all students, were introduced to the lecture course. The goal was for students to develop a more practical understanding and appreciation of hardware design and to improve motivation. Two projects were introduced that involve design of simple digital systems (based on practical applications), design optimization, and physical realization of the system using logic gates and/or memory elements. Two surveys, conducted during the semester, show the benefit of hands-on projects in gaining experience on basic digital hardware design

Configurable digital controllers for smart structural systems using field programmable gate arrays

The objective of the research is to design a flexible, easily configurable, stand-alone smart controller, which could be used for real-time control applications involving smart structures. --Abstract, page iii

Automated Energy Calculation and Estimation for Delay-insensitive Digital Circuits

With increasingly smaller feature sizes and higher on-chip densities, the power dissipation of VLSI systems has become a primary concern for designers. This paper first describes a procedure to simulate a transistor-level design using a VHDL testbench, and then presents a fast and efficient energy estimation approach for delay-insensitive (DI) systems, based on gate-level switching. Specifically, the VHDL testbench reads the transistor-level design\u27s outputs and supplies the inputs accordingly, also allowing for automatic checking of functional correctness. This type of transistor-level simulation is absolutely necessary for asynchronous circuits because the inputs change relative to handshaking signals, which are not periodic, instead of changing relative to a periodic clock pulse, as do synchronous systems. The method further supports automated calculation of power and energy metrics. The energy estimation approach produces results three orders of magnitude faster than transistor-level simulation, and has been automated and works with standard industrial design tool suites, such as Mentor Graphics and Synopsys. Both methods are applied to the NULL Convention Logic (NCL) DI paradigm, and are first demonstrated using a simple NCL sequencer, and then tested on a number of different NCL 4-bit×4-bit unsigned multiplier architectures. Energy per operation is automatically calculated for both methods, using an exhaustive testbench to simulate all input combinations and to check for functional correctness. The results show that both methods produce the desired output for all circuits, and that the gate-level switching approach developed herein produces results more than 1000 times as fast as transistor-level simulation, that fall within the range obtained by two different industry-standard transistor-level simulators. Hence, the developed energy estimation method is extremely useful for quickly determining how architecture changes affect energy usage

Implementation of Design for Test for Asynchronous NCL Designs

In the past two decades, the IC Design industry has set what one might refer to as milestones in the golden era of electronics and computers. Current statistics reveal that the number of gates on a chip in 2005 is 100K compared to 23K just five years back. With the chip density increasing at this rate, there is an inherent need to allow for some efficient testing mechanism on-chip to avail benefits in terms of quality as well as economy. Adding test capabilities to a chip being fabricated increases the initial infrastructure, but the savings that it brings about in terms of cost, time, and maintenance far exceeds the testing cost. In spite of all the innovations, testing asynchronous designs has remained dormant; the reason for this being its inherent complexity. Absence of the global clock signal and presence of more state-holding gates creates a more complex test environment for these designs. The motivation behind this paper stems from the requirement of an efficient testing methodology for a particular class of asynchronous circuits known as Null Conventional Logic (NCL) circuits. The methodology proposed in this paper is easy to use for testing fairly complex designs and is tailored to work with conventional DFT tools

Implementation of Design For Test for Asynchronous NCL Designs

In the past two decades, the IC Design industry has set what one might refer to as milestones in the golden era of electronics and computers. Current statistics reveal that the number of gates on a chip in 2005 is 100K compared to 23K just five years back. With the chip density increasing at this rate, there is an inherent need to allow for some efficient testing mechanism onchip to avail benefits in terms of quality as well as economy. Adding test capabilities to a chip being fabricated increases the initial infrastructure, but the savings that it brings about in terms of cost, time, and maintenance far exceeds the testing cost. In spite of all the innovations, testing asynchronous designs has remained dormant; the reason for this being its inheren