Gate level pipelining optimization, energy estimation, and design for test techniques for asynchronous NULL convention circuits using industry-standard design tools

Authors
Publication date
1 January 2007
Publisher
Scholars\u27 Mine

Abstract

Abstract is not available.

    Similar works

    Full text

    thumbnail-image

    Available Versions

    Missouri University of Science and Technology (Missouri S&T): Scholars' Mine

    redirect
    oaioai:scholarsmine.mst.edu:docto...
    Last time updated on 17/10/2019