1,161 research outputs found
Reconfigurable logic for hardware IP protection: Opportunities and challenges
Protecting the intellectual property (IP) of integrated circuit (IC) design is becoming a significant concern of fab-less semiconductor design houses. Malicious actors can access the chip design at any stage, reverse engineer the functionality, and create illegal copies. On the one hand, defenders are crafting more and more solutions to hide the critical portions of the circuit. On the other hand, attackers are designing more and more powerful tools to extract useful information from the design and reverse engineer the functionality, especially when they can get access to working chips. In this context, the use of custom reconfigurable fabrics has recently been investigated for hardware IP protection. This paper will discuss recent trends in hardware obfuscation with embedded FPGAs, focusing also on the open challenges that must be necessarily addressed for making this solution viable
Invited: High-level design methods for hardware security: Is it the right choice?
Due to the globalization of the electronics supply chain, hardware engineers are increasingly interested in modifying their chip designs to protect their intellectual property (IP) or the privacy of the final users. However, the integration of state-of-the-art solutions for hardware and hardware-assisted security is not fully automated, requiring the amendment of stable tools and industrial toolchains. This significantly limits the application in industrial designs, potentially affecting the security of the resulting chips. We discuss how existing solutions can be adapted to implement security features at higher levels of abstractions (during high-level synthesis or directly at the register-transfer level) and complement current industrial design and verification flows. Our modular framework allows designers to compose these solutions and create additional protection layers
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Flame Retardant Intumescent Polyamide 11 Nanocomposites – Further Study
The objective of this research is to develop improved polyamide 11 and 12 polymers with
enhanced flame retardancy, thermal, and mechanical properties for selective laser sintering
(SLS) rapid manufacturing (RM). In the present study, a nanophase was introduced into the
polyamide 11 and combine with a conventional intumescent flame retardant (FR) additive via
twin screw extrusion. Arkema Rilsan® polyamide 11 molding polymer pellets were used with
two types of nanoparticles such as: chemically modified montmorillonite (MMT) organoclays
and carbon nanofibers (CNFs). Two types of Clariant’s Exolit® OP 1311 and 1312 intumescent
FR additives were used to generate a family of FR intumescent polyamide 11 nanocomposites
with anticipated synergism.Mechanical Engineerin
Using Static Analysis for Enhancing HLS Security
Due to the increasing complexity of modern integrated circuits, High-Level Synthesis (HLS) is becoming a key technology in hardware design. HLS uses optimizations to assist during design space exploration. However, some of them can introduce security weaknesses. We propose an approach that leverages static analysis to identify a class of weaknesses in HLS-generated code. We show that some of these weaknesses can be corrected through the automatic generation of HLS directives. We evaluate our approach by comparing the static analysis results with formal verification. Our results show that the static approach has the same accuracy as formal methods while being 3Ă— to 200Ă— faster
Designing ML-resilient locking at register-transfer level
Various logic-locking schemes have been proposed to protect hardware from intellectual property piracy and malicious design modifications. Since traditional locking techniques are applied on the gate-level netlist after logic synthesis, they have no semantic knowledge of the design function. Data-driven, machine-learning (ML) attacks can uncover the design flaws within gate-level locking. Recent proposals on register-transfer level (RTL) locking have access to semantic hardware information. We investigate the resilience of ASSURE, a state-of-the-art RTL locking method, against ML attacks. We used the lessons learned to derive two ML-resilient RTL locking schemes built to reinforce ASSURE locking. We developed ML-driven security metrics to evaluate the schemes against an RTL adaptation of the state-of-the-art, ML-based SnapShot attack
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Flammability and Thermal Properties of Polyamide 11-Alumina Nanocomposites
Neat polyamides 11 and 12 lack high strength/high heat resistance and flame retardancy.
The incorporation of selected nanoparticles is expected to enhance these properties to a
level that is desired and required for performance driven applications. This enhancement
may result in additional market opportunities for the polyamide 11 and 12 polymer
manufacturers. The objective of this study is to develop polyamide 11 polymer
nanocomposites with enhanced thermal, flammability, and mechanical performance for
selective laser sintering (SLS) rapid manufacturing. Three types of nano-alumnia (X-0
needle, X-25SR, and X-0SR) with different organic treatments were melt-compounded
into polyamide 11 in three different weight loadings of the nanoparticles (2.5%, 5%, and
7.5%). Injection molded specimens were fabricated for thermal, flammability, and
mechanical properties characterization. Although nano-alumina was uniformly dispersed
in polyamide 11 and better thermal stability of the nanomodified materials was observed,
the desired FR characteristics of the nanomodified polyamide 11 was not achieved. None
of the materials passed the desired UL 94 V0 rating.Mechanical Engineerin
Somatic BRCA Mutation in a Cholangiocarcinoma Patient for HBOC Syndrome Detection
BRCA-associated hereditary breast and ovarian cancer syndrome (HBOC) is characterized by an increased risk of developing other malignancies including cholangiocarcinoma (CCA). Somatic BRCA mutations have been reported in CCA, but they have yet to be utilized in a proband case to identify HBOC in families. Two healthy daughters of a deceased female patient who had had metachronous breast cancer and CCA received genetic counseling to assess their cancer risk. Somatic BRCA1/2 mutation analysis was performed by next-generation sequencing on the DNA extracted from a formalin-fixed, paraffin-embedded CCA biopsy specimen of their mother. A pathogenic variant was identified (c.6468_6469delTC in a BRCA2 gene mutation). Germline BRCA mutation analysis of the two daughters detected the same pathogenic variant in one of them. For the first time, a CCA somatic BRCA mutation has been used to identify a family with HBOC
Not All Fabrics Are Created Equal: Exploring eFPGA Parameters for IP Redaction
Semiconductor design houses rely on third-party foundries to manufacture their integrated circuits (ICs). While this trend allows them to tackle fabrication costs, it introduces security concerns as external (and potentially malicious) parties can access critical parts of the designs and steal or modify the intellectual property (IP). Embedded field-programmable gate array (eFPGA) redaction is a promising technique to protect critical IPs of an ASIC by redacting (i.e., removing) critical parts and mapping them onto a custom reconfigurable fabric. Only trusted parties will receive the correct bitstream to restore the redacted functionality. While previous studies imply that using an eFPGA is a sufficient condition to provide security against IP threats like reverse-engineering, whether this truly holds for all eFPGA architectures is unclear, thus motivating the study in this article. We examine the security of eFPGA fabrics generated by varying different FPGA design parameters. We characterize the power, performance, and area (PPA) characteristics and evaluate each fabric’s resistance to Boolean satisfiability (SAT)-based bitstream recovery. Our results encourage designers to work with custom eFPGA fabrics rather than off-the-shelf commercial FPGAs and reveals that only considering a redaction fabric’s bitstream size is inadequate for gauging security
ALICE: An Automatic Design Flow for eFPGA Redaction
Fabricating an integrated circuit is becoming unaffordable for many semiconductor design houses. Outsourcing the fabrication to a third-party foundry requires methods to protect the intellectual property of the hardware designs. Designers can rely on embedded reconfigurable devices to completely hide the real functionality of selected design portions unless the configuration string (bitstream) is provided. However, selecting such portions and creating the corresponding reconfigurable fabrics are still open problems. We propose ALICE, a design flow that addresses the EDA challenges of this problem. ALICE partitions the RTL modules between one or more reconfigurable fabrics and the rest of the circuit, automating the generation of the corresponding redacted design
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