Estimation and uncertainty analyses of grassland biomass in Northern China: Comparison of multiple remote sensing data sources and modeling approaches

Accurate estimation of grassland biomass and its dynamics are crucial not only for the biogeochemical dynamics of terrestrial ecosystems, but also for the sustainable use of grassland resources. However, estimations of grassland biomass on large spatial scale usually suffer from large variability and mostly lack quantitative uncertainty analyses. In this study, the spatial grassland biomass estimation and its uncertainty were assessed based on 265 field measurements and remote sensing data across Northern China during 2001-2005. Potential sources of uncertainty, including remote sensing data sources (DATsrc), model forms (MODfrm) and model parameters (biomass allocation, BMallo, e.g. root:shoot ratio), were determined and their relative contribution was quantified. The results showed that the annual grassland biomass in Northern China was 1268.37 +/- 180.84Tg (i.e., 532.02 +/- 99.71 g/m(2)) during 2001-2005, increasing from western to eastern area, with a mean relative uncertainty of 19.8%. There were distinguishable differences among the uncertainty contributions of three sources (BMallo >DATsrc>MODfrm), which contributed 52%, 27% and 13%, respectively. This study highlighted the need to concern the uncertainty in grassland biomass estimation, especially for the uncertainty related to BMallo. (C) 2015 Elsevier Ltd. All rights reserved

A 10-bit 50-MS/s sample-and-hold circuit with low distortion sampling switches

A fully-differential switched-capacitor sample-and-hold (S/H) circuit used in a 10-bit 50-MS/s pipeline analog-to-digital converter (ADC) was designed and fabricated using a 0.35-μm CMOS process. Capacitor fliparound architecture was used in the S/H circuit to lower the power consumption. In addition, a gain-boosted operational transconductance amplifier (OTA) was designed with a DC gain of 94 dB and a unit gain bandwidth of 460 MHz at a phase margin of 63 degree, which matches the S/H circuit. A novel double-side bootstrapped switch was used, improving the precision of the whole circuit. The measured results have shown that the S/H circuit reaches a spurious free dynamic range (SFDR) of 67 dB and a signal-to-noise ratio (SNR) of 62.1 dB for a 2.5 MHz input signal with 50 MS/s sampling rate. The 0.12 mm~2 S/H circuit operates from a 3.3 V supply and consumes 13.6 mW

A 12bit 300MHz Current-Steering CMOS D/A Converter

The proposed DAC consists of a unit current-cell matrix for 8MSBs and a binary-weighted array for 4LSBs, trading-off between the precision, speed, and size of the chip. In order to ensure the linearity of the DAC, a double Centro symmetric current matrix is designed by the Q2 random walk strategy. To achieve better dynamic performance, a latch is added in front of the current switch to change the input signal, such as its optimal cross-point and voltage level. For a 12bit resolution,the converter reaches an update rate of 300MHz

A Novel Power Supply Solution of a Passive RFID Transponder

This paper presents a power supply solution for fully integrated passive radio-frequency identification(RFID) transponder IC,which has been implemented in 0.35μm CMOS technology with embedded EEPROM from Chartered Semiconductor.The proposed AC/DC and DC/DC charge pumps can generate stable output for RFID applications with quite low power dissipation and extremely high pumping efficiency.An analytical model of the voltage multiplier,comparison with other charge pumps,simulation results,and chip testing results are presented

A Compact Direct Digital Frequency Synthesizer for the Rubidium Atomic Frequency Standard

A compact direct digital frequency synthesizer （DDFS） for system-on-chip implementation of the high precision rubidium atomic frequency standard is developed. For small chip size and low power consumption, the phase to sine mapping data is compressed using sine symmetry technique, sine-phase difference technique, quad line approximation technique,and quantization and error read only memory （QE-ROM） technique. The ROM size is reduced by 98% using these techniques. A compact DDFS chip with 32bit phase storage depth and a 10bit on-chip digital to analog converter has been successfully implemented using a standard 0.35μm CMOS process. The core area of the DDFS is 1.6mm^2. It consumes 167mW at 3.3V,and its spurious free dynamic range is 61dB

A high speed direct digital frequency synthesizer realized by a segmented nonlinear DAC

This paper presents a high speed ROM-less direct digital frequency synthesizer (DDFS) which has a phase resolution of 32 bits and a magnitude resolution of 10 bits. A 10-bit nonlinear segmented DAC is used in place of the ROM look-up table for phase-to-sine amplitude conversion and the linear DAC in a conventional DDFS.The design procedure for implementing the nonlinear DAC is presented. To ensure high speed, current mode logic (CML) is used. The chip is implemented in Chartered 0.35μm COMS technology with active area of 2.0 × 2.5 mm~2 and total power consumption of 400 mW at a single 3.3 V supply voltage. The maximum operating frequency is 850 MHz at room temperature and 1.0 GHz at 0 ℃

Real-Time Method and Implementation of Head-Wave Extraction for Ultrasonic Imaging While Drilling

Extracting head waves and subsequently uploading their results from the downhole to the surface system in real time could improve the real-time guidance of ultrasonic imaging logging while drilling (UILWD) for drilling operations. To realize the downhole real-time extraction of head waves in this logging, three aspects were explored in this study. First, an improved energy ratio head-wave arrival extraction algorithm based on the weighting coefficients and characteristic functions, along with an amplitude detection method relying on peak-to-peak values, was proposed. Second, an echo reception pre-processing analog circuit and a digital signal processing circuit based on FPGA were designed. A pipeline algorithm was developed in FPGA to extract the arrival time and amplitude of the head wave. Finally, software simulations, laboratory tests, and field experiments related to this method were conducted. Our results showed that the real-time head-wave extraction method demonstrated a strong anti-noise ability in real time. The maximum relative error of the arrival time was less than 5%. The relative error of the amplitude was acceptable, and 90% of this value was within 5%. Through the measurement, the time of processing a single-channel waveform by a downhole algorithm was less than 15 ms, thus meeting the requirements for the real-time processing of downholes

A 12-bit 300 MHz CMOS DAC for high-speed system applications

This paper describes a 12-bit 300 MHz CMOS DAC for high-speed system applications. The proposed DAC consists of a unit current-cell matrix for 8 MSBs and a binary-weighted array for 4 LSBs. In order to ensure the linearity of DAC, a double Centro symmetric current matrix is designed by using the Q(2) random walk strategy. To minimize the feedthrough and improve the dynamic performance, the drain of the switching transistors is isolated from the output lines by adding two cascoded transistors