High-field current transport and charge trapping in buried oxide of SOI materials under high-field electron injection, Journal of Telecommunications and Information Technology, 2004, nr 1

Mechanisms of the charge transfer, the charge trapping, and the generation of positive charge during the high-field electron injection into buried oxide of silicon-on-insulator structures fabricated by different technologies are analyzed based on the data obtained from current-voltage, injection current-time, and capacitance-voltage characteristics together with SIMS data. Electron injection both from the Si film and the Si substrate is considered. The possibility of using the trap-assisted electron tunneling mechanisms to explain the high-field charge transfer through the buried oxides of UNIBOND and SIMOX SOI materials is considered. It is shown that considerable positive charge is accumulated near the buried oxide/substrate interface independently from the direction of the injection (from the lm or from the silicon substrate) for UNIBOND and SIMOX SOI structures. Thermal stability of the charge trapped in the buried oxides is studied at temperatures ranging from 20 to 400C. The theory is compared with the experimental data to find out the mechanisms of the generation of positive charge in UNIBOND and SIMOX buried oxides

Field-effect mobility extraction in nanowire field-effect transistors by combination of transfer characteristics and random telegraph noise measurements

A technique based on the combined measurements of random telegraph-signal noise amplitude and drain current vs. gate voltage characteristics is proposed to extract the channel mobility in inversion-mode and accumulation-mode nanowire transistors. This method does not require the preliminary knowledge of the gate oxide capacitance or that of the channel width. The method accounts for the presence of parasitic source and drain resistance effect. It has been used to extract the zero-field mobility and the field mobility reduction factor in inversion-mode and junctionless transistors operating in accumulation mode. (C) 2011 American Institute of Physics. (doi:10.1063/1.3626038

Random telegraph-signal noise in junctionless transistors

Random telegraph-signal noise (RTN) is measured in junctionless metal-oxide-silicon field-effect transistors (JL MOSFETs) as a function of gate and drain voltage and temperature. It is shown that the RTN in JL MOSFETs increases significantly when an accumulation layer is formed. The amplitude of RTN is considerably smaller in JL devices than in inversion-mode MOSFET fabricated using similar fabrication parameters. A measurement technique is developed to extract the main parameters of the traps, including the average charge capture and emission time from the traps. (C) 2011 American Institute of Physics. (doi:10.1063/1.3557505

High-temperature instability processes in SOI structures and MOSFETs, Journal of Telecommunications and Information Technology, 2001, nr 1

The paper reviews the problems related to BOX high-temperature instability in SOI structures and MOSFETs. The methods of bias-temperature research applied to SOI structures and SOI MOSFETs are analysed and the results of combined electrical studies of ZMR, and SIMOX SOI structures are presented. The studies are focused mainly on electrical discharging processes in the BOX at high temperature and its link with new instability phenomena such as high-temperature kink effects in SOI MOSFETs

Functional Nanomaterials and Devices VII

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Nanoscaled Semiconductor-on-Insulator Structures and Devices

Proceedings of the NATO Advanced Research Workshop on Nanoscaled Semiconductor-on-Insulator Structures and Devices, Big Yalta, Ukraine, 15-19 October 2006

Evidence for Substrate Bias effects in SOI ΩFETs

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Metal-Insulator-Metal Single Electron Transistors with Tunnel Barriers Prepared by Atomic Layer Deposition

Single electron transistors are nanoscale electron devices that require thin, high-quality tunnel barriers to operate and have potential applications in sensing, metrology and beyond-CMOS computing schemes. Given that atomic layer deposition is used to form CMOS gate stacks with low trap densities and excellent thickness control, it is well-suited as a technique to form a variety of tunnel barriers. This work is a review of our recent research on atomic layer deposition and post-fabrication treatments to fabricate metallic single electron transistors with a variety of metals and dielectrics